Abstract: A magnetic recording system with a rate 16/17(0,6/8) encoder/decoder modulation code. This modulation code has a low k constraint for synchronization of a road clock of the magnetic recording system. Furthermore, this magnetic recording system has a low hard error rate due to low 3- and 4-byte error propagation. The digital logic circuit for the encoder/decoder system is elegantly simple. Such simplicity reduces propagational delays and circuit size, as measured in number of logic gates. The modulation code is implemented with a decoder that includes a lower byte decoder and an upper byte decoder. An input of the upper byte decoder is in part coupled to and in part decoupled from the lower byte decoder. Similarly, an input of the lower byte decoder is in part coupled to and in part decoupled from the upper byte decoder.

Abstract: An integrated circuit package (10, 40) may comprise an integrated circuit chip (12, 42) and a substrate (14, 44) opposite the chip (12, 42). A connector (20, 52) may be disposed between the chip (12, 42) and the substrate (14, 44) to electrically couple the chip (12, 42) and the substrate (14, 44). A matrix (24, 50) may be disposed about the connector (20, 52). The matrix (24, 50) may comprise a blend of liquid crystal polymer and thermoplastic polymer. The matrix (24, 50) may have a coefficient of thermal expansion in a direction (26, 56) substantially parallel to the chip (12, 42) and the substrate (14, 44) that is greater than that of the chip (12, 42) and that is less than that of the substrate (14, 44) in the substantially parallel direction (26, 56). In a direction (28, 58) normal to the substantially parallel direction (26, 56), the matrix (24, 50) may have a coefficient of thermal expansion that is approximately that of the connector (20, 52).

Abstract: An embodiment of the instant invention is a scanning-probe microscope for measuring the topography of a surface of a sample, the scanning-probe microscope comprising: an XYZ piezo drive (piezo drive 1); a quartz tuning-fork oscillator (fork 2) having a first electrode (electrode 3 or 4) and a second electrode (electrode 3 or 4), wherein the quartz tuning-fork oscillator is attached to the XYZ piezo drive, and wherein the quartz tuning-fork oscillator is oriented such that the tines of the quartz tuning-fork oscillator each lie in the XY plane and their fundamental mode of oscillation vibrates the ends of the tines in the Z direction; a probe tip (probe tip 6) affixed to one of the tines, the probe tip comes to a point in the Z direction and directed away from the XYZ piezo drive; a signal source (source 7) to provide a drive signal to drive the first electrode at a mechanical resonant frequency of the quartz tuning-fork oscillator; a current-to-voltage amplifier (preamp 8) to monitor the electrical current fl

Abstract: A motor starting device (1) has a thermostatic element (14) of a first switch circuit (11), a first resistive heater (13) serially connected to the first switch circuit, a thermostatic element (22) of a second switch circuit (21) and a second resistive heater (23) serially connected to the second switch circuit. The thermostatic element (22) of the second switch circuit is heated by both the first and second resistive heaters and, after actuation, is closer to the first resistive heater (13), thereby bringing the second switch circuit (23) into a de-energized state. When the second switch circuit (21) and the second resistive heater (23) are employed in the motor starting device, it becomes possible to provide a large electric current to the start winding during the start-up phase and to make the electric current that flows to the start winding zero after the start-up phase.

Abstract: A semiconductor device includes a first transistor (52) and gated diode (50) formed at a face of a semiconductor layer (56). The first transistor (52) includes a source region (60a), a drain region (60b), a gate oxide layer (62), and a conductive gate (64). The gated diode (54) includes a first moat region (66a), a second moat region (66b), a gate oxide layer (68), and a conductive gate (70). A first conductor (77) connects the conductive gate (70) of the gated diode (54) to the semiconductor layer (56) and a second conductor (76) connects the moat regions (66a, 66b) of the gated diode (54) to the conductive gate (64) of the first transistor (52). Gated diode (54) has a reduced breakdown voltage relative to the gate oxide layer (62) of first transistor (52) and thus establishes a leakage path to semiconductor layer (56) to direct leakage current to semiconductor layer (56), thereby inhibiting charge from accumulating on the gate oxide layer (62) of first transistor (52).

Abstract: A system and method for detecting anomalies on a manufactured device includes or utilizes a moveable stage for holding and positioning the device, a camera for capturing an image of the device on the stage, a digitizer coupled to the camera for producing a digital-pixel-based representation of the image, and a computer having a processor and memory. The computer is coupled to the digitizer for receiving the digital-pixel-based representation from the digitizer and coupled to the stage for selectively moving the stage to align the device. The computer is programmed to be operable to symbolically decompose a digital-pixel-based representation of an image to create a primitive-based representation of the image. The image may be aligned by the computer with respect to the rotation of geometric objects in the image by developing a histogram of angles and lengths and matching them to determine a rotational shift.

Abstract: An image sensing cell includes: a light sensing device 18; a first transistor 10 having a first node coupled to the light sensing device 18; a second transistor 12 having a first node coupled to a second node of the first transistor 10; a third transistor 14 having a control node coupled to the light sensing device 18; and a fourth transistor 16 having a first node coupled to a first node of the third transistor.

Abstract: A ten transistor low voltage, low power static random access memory cell (10) includes a first inverter (12) cross-coupled to a second inverter (18). A series combination of a first pass transistor (24) and a first bitline select transistor (28) is connected between an output node (13) of the first inverter (12) and a first bitline (36). A first write pass transistor (32) is placed in parallel with the first pass transistor (24). A series combination of a second pass transistor (26) and a second bitline select transistor (30) is connected between an output node (17) of the second inverter (18) and a second bitline (38). A second write pass transistor (34) is placed in parallel with the second pass transistor (26).

Abstract: A design having a semiconductor microchip bonded to a circuit board is described. This design may include: a printed circuit board (58); a semiconductor microchip (56) bonded to the circuit board (58) by means of an adhesive layer placed between the bonding surface of the microchip (56) and the desired bonding site on the circuit board (58); the adhesive layer providing for thermal relief as well as electrical contact between the microchip (56) and circuit board (58), and consisting of two or more concentric regions that adjoin but do not overlap one another; one being a center core region (50) of thermally and electrically conductive material; the other being a perimeter region (54) of thermally conductive and electrically nonconductive material surrounding the center core region (50) such that the perimeter region's (54) inner boundary completely bounds the center core region (50), and such that the perimeter region's (54) outer boundary extends to a lead on the microchip (56).

Abstract: To completely suppress or minimize the voids formed between the insulating substrate and the IC chip in order to prevent the problems of separation and cracking of the chip caused by the aforementioned voids. The present invention is preferably adopted for the Chip Six Package type package or other package types equipped with solder bumps or other external connecting terminals directly beneath the IC chip. For insulating substrate (3), on its chip-carrying surface, there is pattern element (6) in the region beneath the IC chip and free of conductor pattern elements (4) in addition to conductor pattern element (4) for forming electrical connection between the electrode pads and the external connecting terminals of the chip. Said pattern element (6) divides said region into plural small regions A. IC chip (2) is bonded through die paste on insulating substrate (3) such that an end of conductor pattern element (4), pattern element (6) and divided small regions A are covered.

Abstract: A method of reducing power supply current transients in a memory array caused by a simultaneous change in logic state of numerous CMOS digital circuits during a memory write cycle. Write driver enable signals (ENT, ENC) and bitcell enable signals (WBC1-WBC24) are sequentially delayed in time during the write cycle through use of the propagation delay of inverters (INV1-INV24-7). The sequential time delay reduces the number of circuits that are simultaneously changing logic state at any given time during the write cycle. The power supply current transient is transformed from a single, large change in current to a series of smaller changes displaced in time from each other during the write cycle. The ground bounce of the power supply network attributed to the current transient is significantly reduced, such change in ground potential being directly related to the magnitude of the current transient and its rate of change with respect to time.

Abstract: An output stage of an amplifier circuit includes a sinking bipolar circuit 22 for sinking current from an external load 12; a sourcing MOS transistor 14 for sourcing current to the external load 12, a source of the MOS transistor 14 coupled to the sinking bipolar circuit 22 to form a common output node 34; a mirroring MOS transistor 16 having a gate coupled to a gate of the sourcing MOS transistor 14 such that current in the sourcing transistor 14 approximately mirrors current in the mirroring transistor 16; and a current mirror circuit 39 responsive to the mirroring transistor 16 and coupled to control current flow through the sinking bipolar circuit 22.

Abstract: A method for heteroepitaxial growth and the device wherein a single crystal ceramic substrate, preferably Y stabilized zirconia, MgAl.sub.2 O.sub.4, A1.sub.2 O.sub.3, 3C--SiC, 6H--SiC or MgO is cut and polished at from about 1.0 to about 10 degrees off axis to produce a substantially flat surface. The atoms on the surface are redistributed on the surface to produce surface steps of at least three lattice spacings. An optional epitaxially grown ceramic buffer layer, preferably AlN or GaN, is then formed on the substrate. Then a layer of semiconductor, preferably SiC, AlN when the buffer layer is used and is not AlN or GaN is grown over the substrate and buffer layer, if used.

Abstract: A compensated amplifier, for amplifying an input signal applied to an input node to provide an output signal at an amplifier output node. The compensated amplifier includes a first amplifier stage having an internal node as an input thereto and having a first stage output node. Also included is a second amplifier stage coupled to the first amplifier stage, having the input node as an input thereto and providing the output signal at the amplifier output node. A capacitor is coupled between the output node and the internal node.

Abstract: A ball grid array package (10) is provided that includes a heat spreader (14), a stiffener (13), a substrate (16), and a die or chip (12). The stiffener (13) is mounted to the heat spreader (14) and has a cavity formed therein. The stiffener (13) may serve as either a ground plane or a power plane of ball grid array package (10), depending on the desired implementation. The substrate (16) includes a signal plane (30) and a power bus (28) on a first surface and has a cavity formed therein. The substrate (16) is mounted to the stiffener (13) through a second surface. The substrate (16) further having at least one hole formed from the first surface to the second surface and a plurality of solder balls, similar to solder ball (20), to provide an external connection to the ball grid array package (10).

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: A data processing device formed in a single semiconductor chip. The data processing device includes an electronic processor, and on-chip peripheral circuitry ordinarily operative together. Further included, are means for selectively entering externally supplied data into the electronic processor and on-chip peripheral circuitry, for starting and stopping operations of the electronic processor and the on-chip peripheral circuitry independently of each other in an emulation mode of operation.

Abstract: A method and system for autonomously operation a PCI-serial bus interface device (20) in an autonomous mode includes directing circuitry (370) for directing an autonomous boot mode select signal to the data transfer device. Instructions configure registers (36, 38) associated with the data transfer device for autonomous operation of a data transfer device. The directing circuit (370) associates with the data packet transfer device for transferring data to at least one program control list (456) for operating said data packet transfer device in an autonomous mode.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Microprocessor 1 is operable to halt in response to an emulation event with partially completed instructions still in the execution pipeline.

Abstract: An improved ring oscillator (10, 70) includes a first, second and third current starved inverters (12, 14, 16) coupled in a ring, a first fast inverter (40) coupled between the second and third current starved inverters (14, 16), and a second fast inverter (45) coupled between the third and first current starved inverters (14, 16). An output buffer (30) coupled to the ring provides an output periodic waveform.