Abstract: A display system using red, green, blue, and white light. The system derives data for the white portion of a color wheel or a white device from the red, green and blue data. The white portion of the color wheel is controlled as if it were another primary color on the wheel. Errors are prevented by a correction applied if the unfiltered light from the source has a different color temperature than the white light produced using the red, green and blue segments of the color wheel, or the devices for those colors. Analysis is performed on the data to determine if white light is necessary to be added to each frame of data.

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm.

Abstract: A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. These units form an instruction execution pipeline that operates without interlocks so that nestable delayed branch instructions are provided. The control circuitry for the instruction execution pipeline is operable to begin processing a second branch instruction having a second target address on a pipeline phase immediately after beginning processing of a first branch instruction having a first target address.

Abstract: A method is provided for improving the texture of a metal interconnect (32) in a semiconductor device (10). A first layer of titanium (24), a layer of titanium nitride (26), a second layer of titanium (28), and a metal film (30) are sequentially formed over an oxide layer (12). The second titanium layer (28) is preferably out 10-20 nm thick. Because the metal film (30) is formed over the second titanium layer (28), any metal interconnect (32) that is formed as a part of the metal film (30) has a strong (111) crystalline orientation. Furthermore, because the second titanium layer (28) is relatively thin, the metal film (30) and metal interconnect (32) are not completely transformed into a metal compound having a high electrical resistance.

Abstract: A single polysilicon memory cell (10) provides a positive low programming and erase voltage together with a small cell size and includes P substrate (12) and P-well (14) formed within P substrate (12). NMOS transistor (16) is formed within P-well (14). N.sup.+ control gate (26) is formed in P-well (14) and includes punch-through implant region (26). NMOS transistor (16) and N.sup.+ control gate (26) have in common electrically isolated polysilicon gate (22, 32) for operating as a floating gate in common with NMOS transistor (16) and N.sup.+ control gate (26). N.sup.+ control gate (26) includes P-channel punch-through implant (34) for increasing the capacitive coupling ratio. This improves programming and erasing efficiency within single polysilicon memory cell (10).

Abstract: One embodiment of the instant invention is a process chamber for heating a semiconductor wafer, the process chamber comprising: heating elements (elements 104 of FIG. 2a) for providing heating energy; means for holding (means 112 of FIG. 2a) the semiconductor wafer; and shutters situated between the heating elements and the means for holding the semiconductor wafer, the shutters (shutters 108 of FIGS. 2a and 2b and shutters of FIGS. 2c and 2d for blocking the heating energy from getting to the semiconductor wafer when the shutters are in a closed position and for directing the heating energy to the semiconductor wafer when in an open position.

Abstract: In accordance with the present invention, an improved method and structure is provided for integrating polymer and other low dielectric constant materials, which may have undesirable properties, into integrated circuit structures and processes, especially those requiring multiple levels of interconnect lines. Since the bond is typically weak between low-k materials such as polymers 18 and traditional dielectrics such as SiO.sub.2 22, the weak bonding may cause delamination or other problems during subsequent processing. The present invention increases yield and simplifies processing subsequent to application of the low-k material by providing an adhesion/protective layer 20 between the low-k material 18 and the intermetal dielectric 22. A preferred embodiment is a spun-on layer 20 of HSQ cured on a hotplate prior to application of the SiO.sub.2 intermetal dielectric.

Abstract: A tape carrier package having many pins with a fine pitch can be simultaneously attained through a simplified positioning during the connection to external devices. Leads (4) and (5) are formed from an over coat area (3), which is formed at the central area of a base film (2), which is made of a resin, such as polymide, for example. Furthermore, outer leads (4a) at the input side and outer leads (5a) at the output side are respectively formed in a manner so that they extend towards both edge areas of the base film (2). A notched section 6 is formed between the outer leads (5a) at the output side of the base film (2), and through this, each of the regions (2a) and (2b) expands independently during a thermocompression bonding. The notched section 6 is provided almost at the central area of the base film (2) in the longitudinal direction, and outer leads (5) at the output side in the same number (256 for example) are formed at both of its sides in a pitch of approximately 70 .mu.m.

Abstract: An integrated circuit 100 emits light corresponding to a defect in the integrated circuit 100. The light is transformed to electrical signals by a photomultiplier 206. The spectral content of the electrical signals is compared with predetermined or known noise signatures to identify the defects in the integrated circuit 100.

Abstract: An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.

Abstract: Method of control of a three-phase or multi-three-phase invertor (1) supplied from a DC voltage source (2) and controlled by a processor (5) for deriving, in the course of successive slaving periods, signals for pulse-width-modulation control of the transistors of the invertor. It consists, from measuring the power supply current of the invertor and from taking account of the switching states of the transistors, in reconstituting the phase currents.

Abstract: A microprocessor operates in response to microinstructions stored in a read only memory. A patch table stores a indication of patch microinstructions stored in cache memory. This cache memory caches data and/or macroinstructions for the microprocessor. Each new microaddress is compared with the patch table entries. If there in no match, then a multiplexer selects the microinstruction recalled from that microinstruction address within the microinstruction read only memory. If there is a match, then a corresponding patch microinstruction is recalled from the cache memory. The multiplexer selects this patch microinstruction. The microprocessor operates under the control of the selected microinstruction. This technique enables a fix of faulty microinstructions in the field, by supplying the computer user with the patch microinstructions. Using a portion of the cache memory to store the patch microinstructions eliminates any problem with specifying too large or too small a memory for patch microinstructions.

Abstract: Object detection for scene change analysis is performed by a statistical test applied to data extracted from two images taken from the same scene from identical viewpoints. It is assumed that a single change region corresponding to an object that is present in one image but absence in the other is given. In the case of TV data, the test consists of measuring the coincidence of edge pixels in each image with the boundary of the change region. In the case of IR data, the tests consist of measuring the pixel intensity variance within the change region in each image.

Abstract: A clock circuit including an input terminal (300) for receiving a clock signal and a first pulse generator (302) coupled to the input terminal. The first pulse generator is operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of the clock signal. The circuit also includes a second pulse generator (304) coupled to the input terminal, the second pulse generator being operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of the clock signal. A first clock deskewing circuit (306) is coupled between the first pulse generator and a first clock signal output terminal and a second clock deskewing circuit (308) is coupled between the second pulse generator and a second clock signal output terminal.

Abstract: A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Abstract: A silicon-on-insulator structure (10) having a thick buried multi-layer (14) is disclosed herein. The thick buried multi-layer (14) comprises a thermal expansion coefficient matching layer (14b) between two insulator layers (14a,14c). The thermal expansion co-efficient matching layer (14b) comprises a material that more closely matches the thermal expansion co-efficient of the silicon substrate (12). Examples include polysilicon and nitridized oxide.

Abstract: An integrated circuit (IC) configurable as transmitter/receiver includes a method of preventing unauthorized learning and reproduction of an access code as a security measure. When the IC is configured as a receiver and placed in the learn mode, a flag is set in a memory of a microcontroller. If later configured as a transmitter, the microcontroller checks the flag upon power up and if the flag is set, the stored code is randomized so transmission of it is impossible.

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

Abstract: An electronic terminal employs a liquid crystal display for displaying desired characters. The terminal has circuitry for providing attributes to the characters, on a character-by-character basis or on a plurality of characters basis. These attributes include double width, double height, underline, inversion and intensity control. These attributes are formed using minimal additional memory and circuitry.