Abstract: A data output system (100) is disclosed. The data output system (100) includes a number of data output paths (102a-102h) which provide data output signals (DQ0-DQ7) to a data bus. An invert data path 104 provides an invert data signal (INVOUT) that indicates when the data output signals (DQ0-DQ7) have been inverted to reduce the number of transitions on the data bus. A voter circuit (106) determines when data output signal inversion occurs, and includes a local data comparator (132a-132h) associated with each data output path (102a-102h). Each data comparator (132a-132h) compares a current data output signal (D0-D7) with a next data output signal (DN0-DN7), and in response thereto, generates a differential on a pair of data compare lines (138 and 140). The differential on the data compare lines (138 and 140) is amplified by a differential amplifier (136) to generate the invert output signal (INVN) for the following data output cycle.

Abstract: Method of forming a salicide on a gate structure uses sidewall spacers which leave at least 30 percent of the gate sidewall exposed. After metal deposition, which has at least 50 percent step coverage, an anisotropic etch removes some or all of the metal on horizontal surfaces. Silicides formed from this metal layer are conformal, or even thicker on the sides of the gate than on horizontal structures. This achieves low sheet resistance on the gate, while remaining compatible with shallow junctions.

Abstract: A miniaturized integrated sensor (50) useful for indicating the presence of a sample analyte is disclosed. The sensor (50) has a platform (52) with an upper surface (53) and a detector (62), light source (60), waveguide (58), and reflective fixtures (60,62) embedded in the platform (52). The light source (60) is preferably a light emitting diode and sits in a cup-shaped dimple (68) that directs light from the light source (60) toward one of the reflective fixtures (64) to uniformly distribute light across the waveguide (58). The waveguide (58) is coupled to an upper surface (53) of the sensor platform (52) and is coated with a thin film of indicator chemistry (70) which interacts with the sample analyte to produce optic signal changes that are measurable by the detector (62). A lead frame (51) in the platform (52) has pins (54, 55, 56) which provide the interface to the outside world.

Abstract: An IC seating portion (14) of a socket (2) for a semiconductor device (300) is arranged so that the IC terminal leads can engage with contact heads (22) of contact pins (20) mounted in the socket. Each contact pin (20) is arranged in a respective slit (8) formed by partition members (7) providing electrically isolation of the contact pins from one another. Socket (2) has a blocking member (3) which blocks the gaps or slits at their top to prevent IC terminal leads from becoming entangled with the slits or contact pins (20). A stop member (4) is formed in the IC seating portion (14) to facilitate positioning of a semiconductor device (300) on the seating portion and to prevent the IC terminal leads from interfering with contact pins (20).

Abstract: A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the periphery of the wafer for accepting probe pins without contacting the bond pads of the dies. The dies and selector circuits are electrically connected to the probe areas for conducting electrical testing of the dies. The testing occurs by selecting only one die in a particular row and column and maintaining the remaining dies in a standby mode.

Abstract: A voltage multiplier circuit or charge pump circuit for CMOS integrated circuits having high power efficiency, high current drive and efficient area utilization. An embodiment comprises two mirrored sections driven by control signals (PH00, PH01, PH0.sub.-- P; PH10, PH11, PH1.sub.-- P) generated by a logic circuitry which receives, as input signals, an enable signal (en) and a clock signal (clk), wherein each mirrored section includes N stages and each stage comprises a capacitor (C00, C01, C02; C10, C11, C12) having a lower terminal and an upper terminal, the lower terminal is connected to a first switch (INV0, NCH00, NCH01; INV1, NCH10, NCH11) that, in closed condition, couples the lower terminal of the capacitor to ground (GND), said lower terminal of the capacitor being additionally connected to a second switch (INV0, PCH00, PCH01; INV1, PCH10, PCH11) that, in closed condition, couples the lower terminal of the capacitor to the supply voltage (Vpp).

Abstract: The present invention prevents catastrophic failures of a write precompensation circuit from occurring without limiting the precompensation range to a small value and also extends the range of precompensation beyond limits imposed by the duty cycle of the clock signal. The present invention prevents catastrophic failure of the write precompensation circuit by ORing either the input or the output of the comparator and the opposite phase of the clock. The 180 degree delayed clock forces any transitions that would otherwise have been missed. The present invention extends the range of a write precompensation circuit by ORing the clock and the dock delayed by a time td. The extended duty cycle that results is used to generate a longer precompensation delay. A technique is also provided to maintain constant duty cycle over a broad range of data rates.

Abstract: An MDSL modem is provided that is inter-operable with an ADSL modem. The present invention provides a method for modem operation, by dividing available bandwidth for the modem into a plurality of subsets, selecting at least one of the plurality of subsets for use as a communication path, reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, undersampling any received data, and fast fourier transforming the received data to recover the data transmitted. An MDSL modem is provided having circuitry for dividing available bandwidth for the modem into a plurality of subsets, circuitry for selecting at least one of the plurality of subsets for use as a communication path, circuitry for reducing the SNR value used for bit loading for the selected subsets by a predetermined amount, circuitry for undersampling any received data, and circuitry for fast fourier transforming the received data to recover the data transmitted.

Abstract: In the design of an integrated circuit for comparing serial data signals, the number of transistor elements can be reduced by implementing the comparison gate (12) based on the associated truth table rather than by using a general comparison gate component. Using this method, an exclusive OR gate (22) can be implemented using two transistor elements (221, 222), an exclusive NOR gate (52) can be implemented using two transistor elements (521, 522), an AND gate (62) can be implemented using a single transistor element (621), and an OR gate (72) can be implemented using a single transistor element (721). The reduced number of elements used to implement the comparison gates can provide a transistor element saving in the associated circuit.

Abstract: This invention is a test methodology that immediately retests failed chips to recover false tester reads with no loss of test floor capacity during multiprobe production testing of integrated circuit chips on a wafer. This method retests a chip a second time prior to the multiprobe going to the next chip on the wafer, thus eliminating lost time in repositioning the multiprobe.

Abstract: According to one embodiment of the present invention, an output buffer (200) includes a first output driver (86) having a gate oxide protected from voltage changes on an output (16). A second output driver (88) also has a gate oxide protected from voltage changes on the output (16). A level shifter (60) includes at least one cascode device (66, 68, 70, 72) and switches the first output driver (86) according to the values of a data input (12) and an enable input (14). A bias-generation circuit (300) generates a quasi-failsafe voltage that is approximately equal to a chip core voltage when a power supply (4) is supplying the chip core voltage and equal to a portion of the chip core voltage when the power supply (4) is not supplying the chip core voltage. The bias-generation circuit (300) is coupled to a first output cascode (80) coupled to the first output driver (86), to a second output cascode (84) coupled to the second output driver (88), or to the cascode device (66, 68, 70, 72) of the level shifter (60).

Abstract: A method and system for reducing the effects of false contouring and reducing color shading artifacts. An image signal 102 is dithered by the addition of a small noise signal from a noise generator 500. The added noise signal breaks up the edges of homogenous blocks of pixels, causing the created image to appear to have a smooth transition from one region to the next. The image dithering is especially useful in digital color image displays where processing performed on the chrominance portion of the image signal often causes quantization errors which lead to sharp transitions between similar shades when the input image included a smooth transition.

Abstract: An apparatus for controlling an actuator having a moveable member and having a coil that influences movement of the member, by provision of a drive current to the coil in response to a target speed voltage signal. The invention includes an up/down counter, counting at a predetermined count rate and providing a count output. A control unit is provided for controlling the direction of count of the up/down counter depending on whether the voltage across the coil, sensed periodically a first predetermined interval after the drive current to the coil is interrupted, is greater than, or less than, a reference voltage having a predetermined relationship to the target speed voltage. A digital-to-analog converter is provided, responsive to the count output to provide a compensated voltage signal having a voltage corresponding to the count output.

Abstract: A computing device 10 is disclosed herein. A base unit 12 is provided for housing a plurality of computing components and also may include an input/output device such as a keyboard. A display unit 20 can be pivotally coupled to the base unit 12 about a spine 26a. The display unit 20 may include a viewing surface 24. In addition, a flap 50 can be attached to at least one edge of the display 20 and extend outwardly from screen 24. Electronic components 46 may be housed within the flap 50. Alternatively, the electronic components 46 may be housed within the base unit 12 and electrically coupled back to the display units 20.

Abstract: An emulation device which enables a functional circuit to support self emulation. A serial scan testability interface has at least first, second and third scan paths, said first scan path being provided for applying digital information to the functional circuit for use in emulation of the functional circuit. A first state machine connected to said second scan path has a first state selected from among a first set of states. A second state machine connected to said third scan path has a second state selected from among a second set of states. The emulation device performs an emulation command based on a combined first state of said first state machine and second state of said second state machine. The state of the first state machine indicates a primary portion of the emulation command denoting an emulation command class. The state of the second state machine indicates a secondary portion of the emulation command consisting of a subtype within the emulation command class.

Abstract: A logic circuit (18) comprising a first phase domino logic circuit (20) and a second phase domino logic circuit (22). Each of the domino logic circuits comprises a precharge node (20.sub.PN, 22.sub.PN), a coupling device (20.sub.PT, 22.sub.PT) which when conducting couples the precharge node to a precharge voltage (V.sub.DD) during a precharge phase, and a discharge path (20.sub.L and 20.sub.DT, 22.sub.L and 22.sub.DT) connected to the precharge node which when conducting couples the precharge node to a voltage different than the precharge voltage during an evaluate phase. Further, each of the domino logic circuits comprises an inverter (20.sub.IN, 22.sub.IN) coupled to the precharge node and providing an output responsive to a voltage at the precharge node. The output of the inverter of the first phase domino logic circuit is connected to control the conduction of the discharge path of the second phase domino logic circuit.

Abstract: An automated assembly line is operated and controlled by a computer system. The assembly line is comprised of a plurality of machines which are each segmented into its basic unit operations. The segments are then controlled and operated asynchronously with respect to the other segments of the assembly line.

Abstract: A device for sensing light includes: an active pixel sensor 20; a holding capacitor 67 for storing a pixel signal from the active pixel sensor 20; a scanning switch 71 coupled between the holding capacitor 67 and a sense line 80; a switch control line 76 for turning the switch 71 on and off; a logic gate 90 having a horizontal scan shift register input and a strobe input, the switch control line 76 is an output of the logic gate 90.

Abstract: A method is provided for compressing relatively time invariant binary data, such as speech data in a telephone answering device, using statistical analysis of changes in the data. An original record organized into multiple frames of multiple bits each is used to construct an XORed record of the same number of frames and bits. The XORed record has a base frame with the same bit value pattern as a corresponding base frame of the original record, and remaining frames with bit values given by the outputs of an exclusive-OR operation applied to the bit values of corresponding and prior frames of the original record. The bit positions of the XORed record frame set are analyzed and reordered, according to their bit value change activity and used to construct an output record. The output record may have a base frame with the same bit value pattern as the corresponding reordered XORed record base frame.

Abstract: A method of fabricating a semiconductor device and the device. There is provided a substrate (21) of semiconductor material. A gate electrode (25) is formed over the substrate (21) having a sidewall (27) and electrically isolated from the substrate. Source/drain regions (29, 31) are formed in the substrate defining a channel in the substrate extending beneath the gate electrode. One of a pocket region or a halo region (33) extending substantially entirely under the gate electrode and sidewall is then formed. The pocket region or halo region is formed by providing a compensating species which is implanted at the time of the source/drain implant in order to compensate the doping increase under the source/drain caused by the pocket or halo implant. Since the implant dose and range of this compensating implant is comparable to the pocket or halo implant, no penetration of the gate electrode should occur.