Abstract: A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: An apparatus and method for forming thin film aerogels on semiconductor substrates is disclosed. It has been found that in order to produce defect.about.free nanoporous dielectrics with a controllable high porosity, it is preferable to substantially limit evaporation and condensation of pore fluid in the wet gel thin film, e.g. during gelation, during aging, and at other points prior to obtaining a dried gel. The present invention simplifies the atmospheric control needed to prevent evaporation and condensation by restricting the atmosphere in contact with the wet gel thin film to an extremely small volume. In one embodiment, a substrate 26 is held between a substrate holder 36 and a parallel plate 22, such that a substantially sealed chamber 32 exists between substrate surface 28 and chamber surface 30. Preferably, the average clearance between surfaces 28 and 30 is less than 5 mm, or more preferably, less than 1 mm.

Abstract: A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm.

Abstract: A barrier/liner structure (10) and method. First, a porous nitride layer (12) is formed over a structure (18), for example, by metal-organic CVD (MOCVD). Then, the porous nitride layer (12) is exposed to a silicon- (or dopant-) containing ambient to obtain a silicon-(or dopant) rich surface layer (14). Finally, the silicon- (or dopant) rich surface layer (14) is nitrided to obtain a silicon-nitride (or dopant-nitride) enriched surface layer (16).

Abstract: An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detected, the program counter is loaded with a starting address of the block of instructions, which is stored in register 80. Block repeat count register 86 maintains a repeat count. Zero detection circuit 70 delays decrements of register 86 by a number of clock cycles that is equivalent to a pipeline depth for instruction prefetching of a processor connected to program counter 72. The zero detection circuit 70 outputs a loop-end control signal which controls a selector to selectively provide an incremented address or the start address to the program counter. By delaying decrements of register 86, the state of the repeat count is correctly maintained when the processor pipeline is flushed during an interrupt.

Abstract: A read channel circuit (27) for a hard disk drive system (10) includes an analog-to-digital converter (38) having an output (39) which is supplied through a filter (41) to a detector (46) and to a band/error circuit (47). The band/error circuit extracts from the filter output a band value (48) and an error value (49). The band and error values are used by a timing recovery loop (51, 53) to control the operation of the analog-to-digital converter, and are used by a gain recovery loop (51, 54) to facilitate an automatic gain control function for an analog circuit (36). The band/error circuit uses targets and thresholds which are each a power of two, so that a predetermined number of the least significant bits from the output of the filter can be used as the error value, without modification. The band value is determined from the most significant bits of the output of the filter.

Abstract: A method (FIG. 1) of macroblock bit allocation in an MPEG picture encoding which assigns quantization facators according to macroblock quanfization noise immunity and subsequently adjusts quantization factors according to picture level total encoded bit target. Further reassignment of macroblock bits from high PSNR to low PSNR macroblocks.

Abstract: Method of fabricating a narrow linewidth transistor having a low sheet resistance. The transistor may be fabricated in a surface of a semiconductor layer (12). A gate body (14) may be formed separated from an outer surface (16) of the semiconductor layer (12) by a gate insulator (18). The gate body (14) may have an inner surface (20) proximate to the semiconductor layer (12) and an opposite outer surface (22). An insulator layer (30) may be deposited outwardly of the semiconductor layer (12) and the gate body (14). The insulator layer (30) may be anisotropically etched to form side walls (32) adjacent to the gate body (14). The anisotropic etch may cause a residual layer of contaminants (34) to form on the outer surface (16) of the semiconductor layer (12) and on the outer surface (22) of the gate body (14). A protective layer (50) may be deposited outwardly of the residual layer of contaminants (34). Dopants may be implanted into the semiconductor layer (12) proximate to the side walls (32).

Abstract: The present invention includes a circuit for detecting voltage levels in an integrated circuit including a first reference voltage(324), a first differential amplifier(349) having an inverting input terminal connected to the first reference voltage, a non-inverting input terminal and an output terminal, a first transistor (356) having a control terminal connected to the output terminal of the first differential amplifier, having a first current handling terminal connected to a voltage supply terminal and having a second current handling terminal connected to the non-inverting input terminal of the first differential amplifier, a first load (358) device having a first terminal connected to the second current handling terminal of the first transistor and a second terminal, a second load device (360) having a first terminal connected to the second of the first load device and a second terminal connected to a second reference potential, a second differential amplifier (391) having an inverting input terminal, a n

Abstract: A phase/frequency detector (18) includes a first memory circuit (50), a second memory circuit (52), a first set circuit (54), a second set circuit (58) and a reset circuit (56). The first memory circuit (50) provides a first output signal (20) in response to the first input signal (12). The second memory circuit (52) provides a second output signal (22) in response to the second input signal (14). The first set circuit (54) initiates the transition of the first memory circuit (50) to the active state, and the second set circuit (58) initiates the transition of the second memory circuit (52) to the active state. The reset circuit (56) initiates the transition of the memory circuits (50, 52) to the inactive state.

Abstract: A read mask circuit (300) is disclosed. A mask command is shifted through a series of mask latches (308 and 310) to generate the output-enable input (OE.sub.--) of an output driver (306). In synchronism with the mask command, data bits are shifted through a series of data latches (312 and 314) to the data input (DIN) of the output driver (306). To prevent a race condition between the mask command and the data bit that is to be masked (B3), the mask command, when latched in the second-to-last mask latch (308), is used to interrupt the last data latch (314). This prevents the to-be-masked data bit (B3) from being latched in the last data latch (314) and generating an undesirable output data transition by the output driver (306).

Abstract: A data processing apparatus includes control circuitry (15, 73) connectable to a peripheral device (17) for performing an access of the peripheral device, and data processing circuitry (13) connected to the control circuitry. The control circuitry includes synchronizing circuitry (29, 77) for synchronizing the control circuitry with the data processing circuitry after completion of the peripheral access.

Abstract: A method for designing and fabricating an integrated circuit is disclosed. Signal line interconnect widths are determined by performing an electromigration analysis on a trial layout of the integrated circuit. A representative circuit for an integrated circuit is designed and a trial layout is created that includes a plurality of nets. A preprocessor 505 eliminates nets that do not need further validation. An extraction process 510 generates an RC network representation of each remaining net that is to be validated to form a distributed load simulation model. Distributed capacitance and resistance of signal lines is included with load capacitance of receivers to provide an accurate profile of current flow. A profile of current flowing in the signal line of each net is determined by simulating the operation of each net using simulator 517. Peak current, RMS current and average current is determined.

Abstract: A circuit for reducing the stand-by current of semiconductor device is disclosed in a number of embodiments. In a first embodiment, a first conductive line (302), such as a bit line or common capacitor plate in a DRAM, is charged to a first potential in a stand-by state. A second conductive line (304), such as a word line in a DRAM, is driven to the first potential in the stand-by state in the event a short circuit condition exists between the first conductive line (302) and the second conductive line (304). In a second embodiment, a second conductive line (404) in a semiconductor device is 34w isolated from other circuits in the semiconductor device in a stand-by mode. This allows the second conductive line (404) to rise to a short circuit potential in the event a short circuit condition exists between the second conductive line (404) and a short circuit potential.

Abstract: A spatial light modulator (70) comprised of an array of micromirrors (72) each having support post (74). The support post (74) defines support post edges (76) in the upper surface of the mirrors (72). These support post edges (76) are all oriented at 45 degree angles with respect to an incident beam of light from a light source (80) to minimize diffraction of light from the edges (76) into the darkfield optics when the mirrors are oriented in the off-state. The present invention achieves an increased contrast ratio of about 20% over conventional designs.

Abstract: There is disclosed a multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.

Abstract: An integrated circuit (SAI.sub.0) comprises a first SOI transistor (T4) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. The integrated circuit further includes a second SOI transistor (T5) comprising a plurality of nodes, the plurality of nodes comprising a first source/drain, a second source/drain, a gate for receiving a potential to enable a conductive path between the first source/drain and the second source/drain, and a body terminal coupled to a body region disposed between the first source/drain and the second source/drain. In the integrated circuit, one of the plurality of nodes of the first SOI transistor is connected to receive a first differential input signal.

Abstract: The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

Abstract: A wire of predetermined cross section is provided and fed through a capillary having a bore of predetermined shape and sufficiently larger dimensions so that the wire can be fed through the bore without impediment and without being rotatable within the bore. The capillary is applied to the surface to which the bond is to be made with the smallest cross sectional dimension of the wire disposed between the surface to be bonded and any adjacent wires or bonds in order to minimize the possibility of contact with the adjacent wires or bonds. By utilizing a shaped wire having one narrow dimension and one wide dimension, the space between bond locations required to accommodate the wire can be decreased whereas the total current carrying capacity can be the same as in the case of round wires by having the same cross sectional area as the round wire since the wide dimension is directed away from any adjacent bond locations or the like. In other words, the wire to wire clearance is improved by using the shaped wire.

Abstract: A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240).