Abstract: A sample circuit (10) maintains linear operation over frequency. A switchable diode bridge (12) passes the analog input signal when enabled to one terminal of a sample storage capacitor (14). The second terminal of the capacitor is coupled through a closed FET switch (16) to a reference node (18). Once the analog input signal is stored across the capacitor, the FET switch opens before the diode bridge disables. When the second terminal of the capacitor floats and prevents any further charge from altering the sample voltage across the capacitor. When the diode bridge is disabled, the sample voltage across the capacitor does not change. The sample voltage may be amplified and digitized for further processing in the cellular system.

Abstract: A multichip module (10) having one or more IC die (12-18) supports JTAG testing with a plurality of registers (20-26) within each IC die. JTAG testing requires a one cycle delay bypass mode where registers within an IC not under test are bypassed. To support bypass mode when JTAG testing the multichip module on a printed circuit board, a bypass circuit around the multichip module provides the one cycle delay. The bypass circuit monitors the test data signals to the multichip module and enters bypass mode upon detecting a predetermined sequence of logic states during the instruction sequence. Otherwise, the test data signal passes through a plurality of registers within each IC die. The detection may be performed by counting logic states or otherwise monitoring in the instruction sequence.

Abstract: A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written.

Abstract: A controllable resistance circuit (16, 20) changes effective resistance value in response to an external control signal. The control circuit uses a simple current steering mechanism (32, 34, 38, 40, 42, 44, 46, 48) through a fixed resistor (62) to allow uni-directional or bi-directional operation. When configured as a bi-directional device, both ends of the effective resistance circuit (18, 24) are high impedance and therefore float with respect to any power supply. The effective resistance can be set with the control voltage and adjusted with changing conditions.

Abstract: A mixer circuit (10) combines a buffered RF signal with the LO signal at the gate of a mixing transistor (20) for providing sum and difference product terms as the IF output signal. An inductor (46) provides a DC signal path between the source of the mixing transistor and the drain of the buffering transistor (14) to share the same operating current and thereby reduce power consumption in the mixer. The DC path inductor provides a high impedance to block the RF signal and LO signal. A bias circuit (26, 28) sets the bias point at the gate of the mixing transistor to a mid-point value between V.sub.DD and ground potential. In disable mode, the bias point of the mixing transistor is sufficiently low that the LO signal does not have sufficient power to turn on buffering and mixing transistors that could generate mixing products at the IF output.

Abstract: A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.

Abstract: A data transmitter (12) on a data bus (16) keeps its drive transistor (36) at a minimum bias according to the minimum voltage level on the data bus. The current flowing through the drive transistor in response to a data signal, or a proportional current, is mirrored (52, 54) and compared to a current source (60). Any mismatched between the mirrored current and the current source enables a transistor (58) to bias the drive transistor so that it maintains a minimum conduction state. The base of the drive transistor is held one V.sub.be above the minimum voltage on the data bus. The minimum bias on the base of the drive transistor keeps it conducting so that the transition to full conduction is smooth and prevents any sharp transitions that may cause undesired radiated emissions.

Abstract: An Hardware Description Language (HDL) description file (12) is updated without requiring complete re-assignment of all tokens associated with the HDL statements. The design information is maintained as attributes assigned to the tokens (14). The tokens map onto a block diagram (16). As part of an update to the HDL text file (34), the tokens are compared to see which ones if any have changed. The text lines are compared from left-to-right and right-to-left searching for changes in the text file and associated changes in token mapping (36, 38). All tokens inclusive between the left-most change and right-most change is considered to be different. New tokens are assigned and mapped into the block diagram for the HDL elements that change (40). The mapping of old tokens are removed from the block diagram (42). The mappings from token that did not change are maintained (44).

Abstract: A frequency inversion scrambler in a cordless telephone utilizes an integrated high-pass filter (14) between a first stage low-pass filter (12) and modulator (16) to reduce the filter order while maintaining low group delay in the audio signal. The first stage low-pass filter and high-pass filter remove high frequency components and any DC offset from the filtered audio signal. The modulator translates the spectrum of the filtered signal to sum and difference frequencies. A second stage low-pass filter (18) removes the upper portion of the spectrum such that the resulting frequency spectrum is inverted with respect to the original audio signal to prevent eavesdropping of transmissions between the handset and base unit of the cordless telephone. Another frequency inversion circuit (30, 32, 34, 36) in the base unit inverts the frequency spectrum again back to its original state for transmission along telephone lines.

Abstract: Comparator circuit (72) samples a differential input signal at switched capacitor circuit (100). The input signal is stored across capacitors (128, 130, 132, 134). Reference voltages are subtracted from the input signal to produce a difference signal. The difference is compared to a mid-supply reference VMID, and an amplified representation of the signal is produced at the output of differential gain stage (136). Latching output stage (138) uses feedback circuits (204, 211 and 202, 208) to process the amplified signal and to produce a rail to rail representation of the amplified signal at the inputs (146, 148) of SR latch (140). The feedback circuit also powers-down the output stage after processing the amplified signal. Buffer circuits (205, 213 and 214, 212) allow a new signal to be processed by capacitor circuit (100) while the previous signal is being stored in the SR latch.

Abstract: A method executed by a computer program performs cell characterization in a distributed simulation system by partitioning characterization tasks into individual simulations. A simulation job is generated based on the individual simulations and placed into a simulation job queue. The simulation job queue is copied into a database. The simulation job is accessed and processed in a remote simulator. The remote simulator returns a simulation status and simulation results which are placed into an acknowledge queue. The simulation process is repeated upon detecting an error condition from the simulation status. The simulation status is read from the acknowledge queue and the acknowledge queue is copied into the database.

Abstract: A FIFO uses a fill indicator circuit to indicate a fill status and provide control signals to a data source and data sink to cease operation. A serial string of FIFO cells propagates data from input to output by sending request and acknowledge signals between adjacent cells. The request signal initiates data transfer to the next logical cell and the acknowledge signal indicates completion of the transfer. The fill indicator has one cell for each FIFO cell for monitoring the request and acknowledge signals looking for predetermined state sequences to indicate whether each FIFO cell is full or empty.

Abstract: A digital bus is driven to the logic state of a data input signal upon activating a data enable signal. A bus keeper enable signal activates a buffer having its input and output connected to the digital bus. The data is thus buffered and driven back onto the digital bus during the active state of the bus keeper enable signal in order to retain the logic state after the data enable signal deactivates. The bus keeper enable signal remains active until a subsequent data enable signal becomes active thereby retaining the data on the bus potentially indefinitely.

Abstract: A resistance measuring circuit (10) generates a predetermined reference voltage and impresses that reference voltage across a squib detonation device (12). The resulting current flowing through the squib is mirrored by a current mirror (42,52,54) for providing multiple mirrored currents. The mirrored currents are compared to known current sources (58,60). The output signals go high or low depending on whether the mirrored currents are greater than or less than the fixed current sources. The output signals provide an indication as to whether the measured squib resistance is within a specified resistance range. The current sources may be precisely matched to maintain high accuracy in measuring the resistance.

Abstract: An amplifier (10) receives a bias voltage to the gate of a depletion mode field effect transistor (12). In one embodiment, a bias circuit (20) offsets (22) the bias voltage from a power supply potential (26) to maintain substantially constant drain current over a range of threshold voltages (34,36,38) caused by process and temperature variation. In an alternate embodiment, a transistor (58) in the bias circuit (50) provides an incremental current flow to compensate the bias voltage of the MESFET for variation in threshold voltages. The bias circuit is applicable to other depletion mode field effect transistor circuits having a negative threshold voltage.

Abstract: A method executed by a computer simulator measures energy dissipation in a cell having one or more outputs. A first series of simulations is performed with given cell parameters over a simulation period while varying capacitance on a first output of the cell for providing a first range of currents sunk by the cell. A second series of simulations provides a second range of currents by varying capacitance on a second output. The first and second ranges of currents are converted to first and second ranges of energy dissipations. The energy dissipation due to the charging rates is subtracted from energy dissipation due to the switching for providing a model of energy dissipation by the cell itself. A nominal point of the first range of energy dissipation may be subtracted from each point of the second range of energy dissipation for providing an offset range of energy dissipations.

Abstract: A CMOS amplifier input stage (10) has an n-channel differential input transistor pair (12, 14) and a p-channel differential input pair (26, 28) for receiving an input signal (V.sub.p, V.sub.m). Each transistor pair is respectively coupled to current shunt transistors (20, 32) and to current source transistors (16, 30) that generate currents that are inversely proportional to transistor mobilities. Bias generators (24, 34) apply a voltage to the gates of the shunting transistors respectively. When the input stage receives a common mode signal equal to the voltage applied by the bias generators, three-fourths of transistor (16) current flows through shunt transistor (20). Likewise, three-fourths of transistor (30) current flows through shunt transistor (32).

Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer data through the flipflop. When the data compressor is reset, the CAM array may locate matches in the unused portion which are interpreted as the reset character. A barrel shifter in the data compressor converts variable length codewords into fixed length for transmission. A barrel shifter in the data decompressor converts fixed length codewords back into variable length for decoding into the vocabulary table.

Abstract: A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

Abstract: A low power consumption semiconductor memory device that can read stored data at a faster access time, while minimizing power consumption is provided. In accordance with the logic states on a pair of bit lines on which an information signal stored in the memory cell and an inverted version of that information signal are placed, it is detected that the information signal is placed onto the bit line, and then the information signal on that bit line is read onto the data signal bus.