Abstract: A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.

Abstract: A demodulator circuit (100) and method for producing a demodulated signal V.sub.OUT from an input signal V.sub.IN. A frequency detection circuit (101) produces a quadrature signal V.sub.QUAD which is compared to the input signal V.sub.IN to produce a detected output signal. The phase and frequency of the quadrature signal V.sub.QUAD are responsive to a control signal I.sub.CONTROL. The demodulator circuit (100) has an output terminal (114) which provides the demodulated signal V.sub.OUT. Nonlinearity in the demodulated output signal V.sub.OUT in relation to a modulating signal is reduced by a linearizing feedback circuit (102). Automatic tuning is provided by a tuning feedback circuit (103). The output signals produced at the respective output terminals (114) and (113) of the linearizing feedback circuit (102) and tuning feedback circuit (103) are summed to produce the control current I.sub.CONTROL.

Abstract: A cordless telephone has receive (12) and transmit (14) signal paths for passing voice signals. Sidetones normally appear in the receive signal path from the near party's voice. A signal strength comparator (34) monitors the transmit signal path and the receive signal path and asserts a gain control signal when the transmit path signal strength exceeds a threshold set to a predetermined value below the receive path signal strength. The gain control signal decreases the gain (42) in the receive signal path to reduce undesirably loud sidetones in the speaker earpiece. When the transmit path signal strength is less than the predetermined threshold, the gain control signal is not asserted allowing maximum amplification in the receive signal path as the sidetone is sufficiently small as to not interfere with the main received voice signal, or otherwise become noticeably loud in the speaker earpiece.

Abstract: A multi-crystal controlled oscillator (10) and method includes a first crystal resonator (11), second crystal resonator (14), oscillator circuit (23), and a switch (29). The switch (29) is coupled between the first crystal resonator (11) and the oscillator circuit (23) and between the second crystal resonator (14) and the oscillator circuit (23), and electrically couples either the first (11) or the second crystal resonator (14) to the oscillator circuit (23) in response to a crystal select input (XTAL SELECT).

Abstract: RSD n-bit analog-to-digital converter (10) receives voltage VIN that is compared to reference voltages VH and VL in the first stage (18). A digital code, representing VIN, is generated at first stage outputs (24, 26). First stage residue voltage V22 is compared to VH and VL in the second stage (30). A digital code generated at the outputs (28, 32) of the second stage, represent residue voltage V22. Residue voltage V22 is recycled through the first and second stages. Upon reaching the n.sup.th conversion bit, residue voltage V22 of the n.sup.th -1 bit is compared to second stage mid-level voltage reference VMID. A digital code generated at the outputs of the second stage represents the n.sup.th -1 bit residue voltage V22. The digital codes are stored in storage elements (34) and added in a binary adder (38) to provide the n-bit representation of VIN.

Abstract: An artificial neural network performs error correction on an input signal vector. The input signal vector is process in a forward direction through synapses in each of a plurality of neurons for providing an output signal from each of the neurons. The output signals from the neurons are monitored until the one having the greatest activity level is identified. A reverse flow signal having a predetermined magnitude is processed in the reverse direction through the neuron having the greatest activity level for updating the input signal vector. Alternately, the output signals of competing neurons may be applied through synapses weighted to favor the neuron having the greatest output signal activity. Thus, the neuron with synapses most closely matched to the elements of the input signal vector overpowers the remaining neurons and wins the competition.

Abstract: A pulse separator 110 predicts the start of a vertical synchronizing pulse in a video composite synchronizing signal (VCSS) applied via input 105. At a predicted time, the pulse separator 110 provides a start signal via a first output to the bistable 125, thereby causing a signal at output 130 to vary from a first output level to a second output level. When the end of the vertical synchronizing pulse is detected in the VCSS, a stop signal is provided via a second output to the bistable 125, thereby causing the signal at the output 130 to vary from the second level to the first level. A multiplexer (MUX) 615 switched to couple horizontal synchronizing pulses from input 605 to output 620, when a vertical synchronizing pulse is received from input 625, and, switched to coupled pseudo horizontal synchronizing pulses from pseudo pulse generator 610 to the output 620 when a vertical synchronizing pulse is not received from the input 625.

Abstract: An electronic key validation process increases security by encrypting the security access codes. A key (10) receives data having a hidden polynomial select code and polynomial seed from a host (12). A locally stored (24, 26) select offset and seed offset in the key identifies the location (22) of the select code and seed in the data. The select code decodes (32) into polynomial coefficients which are used to configure a polynomial generator (34). The seed is loaded into the polynomial generator as a starting point of the polynomial. The polynomial generator is clocked a number of cycles to calculate a remainder. The select code is modified (28) to select a new polynomial, and the polynomial generator is clocked another number of cycles. The host runs a similar encryption algorithm. The remainder is sent to the host where it is compared with the host generated remainder for key validation.

Abstract: A electrical flame-off (EFO) wand 200 for emitting an electrical discharge to form a length of bonding wire into a ball comprising a stainless steel tube mounting section 305 for mounting, a platinum rod electrode 315 inserted partially into the tube 305 and secured with electrically conductive epoxy 310. The dimensions of EFO wand 200 allows the capillary 110 to be positioned close to the die-lead frame assembly, improving the productivity of the bonding process and providing economical, good quality and more reliable wire bonding.

Abstract: A band-gap voltage reference (39) has a regulator portion (70) providing a substantially constant current of predetermined magnitude Ic and a band-gap reference portion (72) receiving Ic. The reference portion (72) has a first branch including a first transistor (52) of a first type serially coupled to a second transistor (55) of a second type, a second branch including a third transistor (53) of the first type serially coupled to a fourth transistor (56) of the second type, the first and second branches forming a current mirror (73) carrying a total current of about Ic/2, and a third branch (57) in parallel with the first and second branches and carrying a current of substantially Ic-Ic/2. Base current (65) in the first two branches is compensated by base current (64) of the third branch.

Abstract: A compensating circuit (8) is used with a switched capacitor circuit (10) which includes a switched capacitor arrangement (12) and an op-amp (1) having a first input (14) coupled to a switched capacitor (11), a second input and an output (16). A sampling circuit (19,17,23) samples an error signal at the first input (14) of the op-amp (1) and an amplifier (15) coupled to receive the sampled error signal provides a compensation signal in dependence upon the sampled error signal. The compensation signal provides an offset signal for the second input of the op-amp (1), such that propagation of the error signal to the output (16) of the op-amp (1) is substantially reduced.

Abstract: A battery monitoring circuit (10) sequentially samples individual voltages across a string of serially coupled battery cells (12-18). A control circuit (32) controls first and second multiplexers (34,42) to sample each battery voltage for an over-voltage condition. A comparator (52) detects an over-voltage condition by comparing a divided down battery voltage against a reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (26) in the battery cell conduction path. The battery cells are further sequentially sampled for an under-voltage fault. The comparator detects an under-voltage condition by comparing a second divided down battery voltage against the reference. The conduction path through the battery cells is disabled upon detecting a fault condition by a transistor (24) in the battery cell conduction path.

Abstract: A telephone line interface circuit has a transmit path for coupling to a telephone line and a receive path for coupling to the telephone line (2). The transmit path includes a first amplifier (A1) having an output for coupling to the line (2), a first input for receiving a signal to be transmitted and a second input for receiving a first sum signal made up of a.c. and d.c. line voltage signals plus a.c and d.c. line current signals. The feedback loop thus described has sufficient loop gain to constrain the first sum signal to be substantially equal to the signal at the first input. The receive path includes a second amplifier (A4) having a first input for receiving the first sum signal, a second input for receiving substantially twice a second sum signal made up of the a.c. and d.c. line current signals plus the d.c. line voltage signal/and an output for providing receive signals.

Abstract: A television vertical timebase circuit includes an arrangement (10, 25, 30, 35, 40, 45) for generating a vertical ramp voltage of first and second slopes corresponding to 4:3 and 16:9 aspect ratios. An arrangement (50,55,65) adds a predetermined voltage to a predetermined portion of the 16:9 ratio ramp voltage such that unwanted visible signals are positioned outside the visible screen area when displaying 16:9 aspect ratio pictures.

Abstract: A lateral transistor (14) is configured as a reverse protection diode that allows low and high current modes of operation while maintaining low forward voltage drop. The base region (38) of the lateral transistor is formed inside a collector ring (34) and adjacent to the emitter region (36). In low current mode, the transistor operates as a conventional diode. In high current mode, the excessive number of minority carriers injected into the base region causes the device to enter conductivity modulation that effectively increases the doping concentration and lowers the bulk resistance. The lower bulk resistance keeps the forward voltage drop low. By having the base region inside the collector ring, the bulk resistance is kept low to aid in the onset of conductivity modulation. Thus, the transition between low current mode and high current mode is minimized.

Abstract: A scheduling editor graphically displays an algorithmic description and associated scheduling data (14) on a computer terminal (20) to provide a visual representation of the present clock-based timing and scheduling criteria assigned to the algorithmic description. The graphical display and update of scheduling data is performed by software on a computer system. The software allows the algorithmic description to be modified in a user friendly graphical format to edit the timing and scheduling data before the actual circuit schematic is generated. The design database includes control parameters such as selection of clock signal, execution phase of the selected clock, scheduling type, synchronization type, and concurrent operation that dictate how the scheduling is implemented. The software receives new control parameters selected by the designer via the graphic interface and updates the design database accordingly (16).

Abstract: A bit stream unpacking circuit (10) parses data fields from a serial bitstream as an initial step in decompression. The protocol of the incoming packed data stream is stored in a control ROM (24). As each packed data field arrives, the control ROM provides size and condition instructions (18) to parse out the fields from the serial data stream and store the fields in data storage (14) for later retrieval. The size instruction determines the length of the field in the incoming data. A counter (26) counts clock signals of the incoming serial bitstream and matches the count with the size instruction to determine when a data field has arrived. The condition instruction determines the next address in the control ROM based on the incoming bitstream. Once the incoming message has been parse out and stored, the individual data field may be read directly from the data storage for decompression.

Abstract: A compensation circuit (26, 27, 28, 29) supplies base currents to a plurality of current sources (22, 25) attached to a regulator (50), thereby reducing the load on the regulator and improving overall circuit performance. The compensation circuit measures a single base current, multiplies it by the number of current sources to be supplied, and then provides the multiplied current to a base bus (40) coupled to the bases of the plurality of current sources. The compensation circuit has a very high output impedance with essentially no variation with supply voltage.

Abstract: A method executed by a computer for performing numerical optimization of arbitrary functions in a computer model using parallel processors (10, 12, 14). The method initializes (20) each processor with an initial estimate of the parameter value to be optimized. The initial estimate is evaluated (22) in each processor to determine a solution. A best estimate of the parameter value from the result in each processor is selected (24), and one or more of the parallel processors with the best estimate is set to run in gradient mode while the remaining processors run in random mode (26). The estimates of the parameter value from the processors running in random mode is evaluated until a local minimum is obtained from the processor running in gradient mode (28). The process is repeated until an optimal solution is found (34).

Abstract: An integrated circuit chip includes a processor (4) and a memory (10) coupled by data and address buses (PAB, PDB). The memory is switchable between a first, standard, mode of operation in which a memory controller (14) is operative and a second, cache, mode of operation in which a cache controller (12) is operative by a switch (16, 22, 40). A memory area includes a valid bits array (VBA), a bit of which is set when a valid word is stored in a respective memory address of the memory in standard mode. If a valid bit exists corresponding to an address on the address bus, then information loaded into the memory in standard mode can be used by the processor in cache mode. The operating mode of the memory is switched using an operating mode register having a cache enable section, and a cache enable control line coupled to the memory. A reset arrangement is provided for resetting the valid bits array to flush the cache in a single operation.