Patents Represented by Attorney, Agent or Law Firm Robert D. Atkins
  • Transfer layer of the ATM type and method for operating a transfer switch
    Patent number: 5892755
    Abstract: A transfer layer of an ATM type used between a switch (216) and a number N of communication channels (218). Each communication channel (218) has second storage arrangement B.sub.0, . . . , B.sub.N-1 for storing cell queues having a length of up to P cells each, one of the second storage arrangements being in a busy condition if a minimum number M of cells is stored therein, where M is lesser of equal P. Each communication channel is assigned to one of the switch queues. The transfer layer (217) has third storage arrangement T for storage of a cell queue having a length of up to L cells. Furthermore the transfer layer (217) selectively disables the input of a cell from one of the switch queues into the third storage arrangement if the second storage arrangement is in a busy condition.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: April 6, 1999
    Assignee: Motorola, Inc.
    Inventors: Yaron Ben-Arie, Roni Eliyahu, Ronen Shtayer, Yehuda Shvager
  • Method for shaping a pulse width and circuit therefor
    Patent number: 5892380
    Abstract: A phase-frequency detector (12) is configured for operating at a high frequency. A transition of a clock signal (REF CLK) is detected by a first latch (52) and a signal UP is generated. A transition of a feedback signal (FBK) is detected by a second latch (56) and a signal DOWN is generated. An logic circuit (64) detects the signals UP and the DOWN and generates a reset signal (RESET). A pulse-width of the reset signal (RESET) is controlled and limited by the logic circuit (64) to provide a faster response time for setting the first and second latches (52 and 56) to a state that allows detection of the phase and frequency differences between the clock signal (REF CLK) and the feedback signal (FBK).
    Type: Grant
    Filed: August 4, 1997
    Date of Patent: April 6, 1999
    Assignee: Motorola, Inc.
    Inventor: Brent W. Quist
  • Transistor protection circuit and method
    Patent number: 5892379
    Abstract: A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.
    Type: Grant
    Filed: June 2, 1997
    Date of Patent: April 6, 1999
    Assignee: Motorola, Inc.
    Inventors: Juan Buxo, Andreas A. Wild, Gary H. Loechelt, Thomas E. Zirkle, E. James Prendergast, Patrice M. Parris
  • Transfer rate controller and method of operation
    Patent number: 5889763
    Abstract: A transfer rate controller (10) allows the originator of the data to determine when the data is transferred on the communications link. A method of regulating the transfer of ATM cells to maintain rate precision and provide flexibility for dynamically adjusting the rates at which cells are transferred has been described. In accordance with information on the chronology of prior transfers, cell loss priority, set of rate parameters, traffic types, and priorities, a scheduler (12) determines and schedules the relative ordering or placement of virtual connections with respect to one another. The finder (14) selects virtual connections for data transfer. Therefore, the transfer rate controller (10) provides individual transfer rates to virtual connections in accordance with the type of data traffic transferred.
    Type: Grant
    Filed: June 4, 1996
    Date of Patent: March 30, 1999
    Assignee: Motorola, Inc.
    Inventors: Timothy Glenn Boland, Martin Ludwig Dorr, Alan Gary Ellis
  • Method and apparatus for synchronizing a plurality of output clock signals generated from a clock input signal
    Patent number: 5886562
    Abstract: A clock circuit for generating alternate clock phases (P.sub.1, P.sub.2) whose trailing edges define sampling points of an analog-to-digital converter (106). Complementary signals (CLOCK0, CLOCK1) are generated from a system clock (F.sub.SYS) and switched through transmission gates (340-341, 342-343) when an enable signal (V.sub.EN) is applied. The system clock (F.sub.SYS) is delayed by a delay circuit (316) to produce the enable signal (V.sub.EN) after the complementary signals (CLOCK0, CLOCK1) are stable, thereby synchronizing the complementary signals (CLOCK0, CLOCK1) with the enable signal (V.sub.EN).
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Douglas A. Garrity, Danny A. Bersch
  • Method of reflowing solder bumps after probe test
    Patent number: 5886362
    Abstract: An integrated circuit die is tested by inserting test probe needles into flat solder pads before reflow. The testing is performed at different temperatures to functionally test the integrated circuit die. The solder pads are flat during probe test to improve the uniform contact point and pressure for the test probes, and help avoid slippage or sliding. The probe needles may cause indentation in the solder pads. Following probe test, the solder pads are reflowed to transform the solder pads into solder bumps. Reflow after probe test removes any indentations from the solder pads created during the probe test and leaves only rounded solder bumps without probe damage. The solder bumps are used to flip-chip interconnect the IC into end user systems.
    Type: Grant
    Filed: December 3, 1993
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Lavoie R. Millican, Vern H. Winchell, II
  • Static random access memory cell having graded channel metal oxide semiconductor transistors and method of operation
    Patent number: 5886921
    Abstract: An SRAM memory cell (40) uses GCMOS transistors (42, 44, 56, and 58) for improving discharge of complementary bit lines (60 and 62). The GCMOS transistors (42, 44, 56, and 58) have a graded-channel region on only the source side of the transistors. Configuring the pass-transistors (56 and 58) having the drain terminals connected to the complementary bit lines (60 and 62) and the cross-coupled transistors (42 and 44) having drain terminals connected to the memory cell outputs improves timing for a read operation of the memory cell (40).
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Robert B. Davies, James S. Caravella, Andreas A. Wild, Merit Y. Hong
  • Circuit and method of controlling mixer linearity
    Patent number: 5886547
    Abstract: An integrated receiver circuit (10) has a first amplifier (12) coupled for receiving a radio frequency (RFIN) input signal. A mixer (16) has an RF input coupled to an output of the first amplifier, a local oscillator (LO) input coupled for receiving an LO signal, and an output for providing an intermediate frequency (IF) signal. A second amplifier (20) has an input coupled for receiving the IF signal, and an output for providing a receive signal strength indicator (RSSI) signal representative of an input power level of the receiver signal path. A feedback circuit (22-26 or 72, 78) is coupled between the first output of the second amplifier and a linearity control input of the mixer for controlling linearity of the mixer.
    Type: Grant
    Filed: December 16, 1996
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Jeffrey C. Durec, William E. Main
  • Variable conducting element and method of programming
    Patent number: 5886920
    Abstract: A variable conducting element (10) and method for programming a constant current or constant resistance provided at output terminals (24 and 26) of a ferroelectric transistor (12). The ferroelectric transistor (12) has portions of a ferroelectric material (32A) programmed having up-polarization states separated by domain walls (34) from portions of a ferroelectric material (32B) programmed having down-polarization states. The portion of the ferroelectric material (32A) programmed in the up-polarization state forms current conduction channels between a source region (23) and a drain region (25) of the ferroelectric transistor (12). The ferroelectric transistor (12) is programmed through a capacitor (14) to adjust the charge supplied to a control terminal (22) of the ferroelectric transistor (12).
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Daniel S. Marshall, Jerald Allen Hallmark, David J. Anderson, Ellen Lan
  • Packaging apparatus and method
    Patent number: 5875897
    Abstract: A packaging system (100) protects integrated circuit devices (106) from corrosion and mechanical damage. The devices are enclosed in a reel (102) having a hub (114) in which a cavity (116) is formed for retaining a molded desiccant (118). Apertures (120) between the cavity and the devices provide a vapor path for drawing moisture from the devices. A banding strip (108) for enclosing the devices within the reel has recessed areas (142) for housing pellets of desiccant (140). The reel is placed in an inflatable envelope (50) that includes view ports (56) for reading identifying information on the reel. A vacuum is drawn and the envelope is sealed. Air cells (52) in the inflatable envelope are inflated to cushion the devices from mechanical damage during shipment.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: March 2, 1999
    Assignee: Motorola, Inc.
    Inventors: William V Duncan, Richard J. Barton
  • Ferroelectric semiconductor device and method of manufacture
    Patent number: 5874755
    Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: February 23, 1999
    Assignee: Motorola, Inc.
    Inventors: William J. Ooms, Jerald A. Hallmark, Daniel S. Marshall
  • Power conversion integrated circuit and method for programming
    Patent number: 5859768
    Abstract: A single input pin (48) provides multi-functional features for programming a power supply (10). By connecting the appropriate interface circuit (92, 100, or 112) to the single input pin (48), the power supply (10) is programmed for specific behaviors during power up and toggling of an on/off switch (96, 108). In one mode of operation a light emitting diode (106) in the interface circuit (100) is optically coupled to a microprocessor for signaling the closure of the on/off switch (108), allowing the microprocessor to control the power supply (10) through an opto-coupler (102). In another mode of operation, the single on/off switch (96) controls the power supply (10). In yet another mode of operation, Zener diode (118) in the interface circuit (112) controls the power supply (10) during brown-out and black-out conditions.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: January 12, 1999
    Assignee: Motorola, Inc.
    Inventors: Jefferson W. Hall, Jade H. Alberkrack
  • Ferroelectric semiconductor device and method of manufacture
    Patent number: 5851844
    Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (15) of ferroelectric material disposed on a semiconductor substrate (11) and a gate structure (27) formed on the semiconductor substrate (11). A source region (23) and a drain region (24) are formed on the semiconductor substrate such that the source region (23) and the drain region (24) are laterally spaced apart from the gate structure (27).
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: December 22, 1998
    Assignee: Motorola, Inc.
    Inventors: William J. Ooms, Jerald A. Hallmark
  • Method of manufacturing a ferroelectric device
    Patent number: 5846847
    Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) is manufactured from a substrate (11) that has a layer (14) of ferroelectric material sandwiched between a substrate (13) and a layer (16) of silicon. A gate structure (24) is formed on the layer (16) of silicon. A source region is formed in a portion of the layer (16) of silicon adjacent one side of the gate structure (24) and a drain region is formed in a portion of the layer (16) of silicon adjacent an opposing side of the gate structure (24).
    Type: Grant
    Filed: November 7, 1996
    Date of Patent: December 8, 1998
    Assignee: Motorola, Inc.
    Inventors: William J. Ooms, Jerald A. Hallmark, Daniel S. Marshall
  • Method and apparatus for modeling process control
    Patent number: 5841660
    Abstract: A method for process control which uses discrete lots in which each lot is uniquely identified. The process is modeled with a precedence rule which allows concurrent processing of each discrete lot. Lots are processed simultaneously within different processing steps in such a way as to maintain the unity of the lot while tracking the lot at all times during processing.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 24, 1998
    Assignee: Motorola, Inc.
    Inventors: Jeffrey A. Robinson, Udey Chaudhry, Timothy L. Olson
  • Polarity detector
    Patent number: 5831455
    Abstract: A polarity detector 100 wherein bistables 105 and 107 selectively sample the sequence of pulses and store samples. The samples and the output signal 125, stored by the bistable 109, are compared by the logic circuit 108. When the stored samples have identical polarity and the polarity of the output signal 125 is not identical to the polarity of the samples, then the polarity of the output signal 125 is changed to the polarity of the samples. However, when the polarity of the samples and that of the output signal 125 are not identical, then the polarity of the output signal 125 remains unchanged. In addition, when the polarity of the stored samples are not identical, the polarity of the output signal 125 remains unchanged. Hence, the polarity of the output signal 125 indicates the polarity of the sequence of pulses 120.
    Type: Grant
    Filed: April 15, 1996
    Date of Patent: November 3, 1998
    Assignee: Motorola, Inc.
    Inventor: Yung-Jann Chen
  • Current mode transceiver circuit and method
    Patent number: 5832370
    Abstract: A transmitter (300) sends a transmitted current (I.sub.203, I.sub.204) along a transmit signal path (203, 204) to a receiver (400) having a low input impedance. The receiver includes a transistor structure (402, 404) that amplifies the transmitted current and feeds it back to the input of the receiver to maintain the low input impedance and a substantially constant voltage on the transmit signal path. The substantially constant voltage at the input of the receiver avoids interference with other circuits (206, 208) located along the transmit signal path.
    Type: Grant
    Filed: September 26, 1996
    Date of Patent: November 3, 1998
    Assignee: Motorola, Inc.
    Inventors: Jesus S. Pena-Finol, Mark J. Chambers, Erica G. Miller, Philippe Gorisse
  • Memory programming circuit and method
    Patent number: 5828607
    Abstract: A circuit and method modify data stored in a storage element (30) of a memory circuit (110) when high voltages used for such modification exceed transistor breakdowns. A charge pump (302) produces a pumped voltage (V.sub.P1) for modifying the data. A monitor circuit (304) produces an enable signal (V.sub.PEN) to activate other power supply voltages when the pumped voltage reaches a predetermined voltage level for allowing the data to be modified. A routing circuit (832) selects between the pumped voltage and a first voltage (V.sub.DD) in response to a first control signal (HVENABLEP) to produce a selected voltage. A switching circuit (802-808) passes the selected voltage to the storage element (30) to modify the data when the first supply voltage is selected by the routing circuit.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: October 27, 1998
    Assignee: Motorola, Inc.
    Inventors: Thomas P. Bushey, James S. Caravella, Jeremy W. Moore
  • System and method of communicating between trusted and untrusted computer systems
    Patent number: 5828893
    Abstract: A computer network comprising a trusted computer network (16), and an untrusted computer network (17). A plurality of firewall systems (21) provide controlled access between the trusted computer network and the first untrusted computer network. An Application layer bridge (22) establishes a transparent virtual circuit across the plurality of firewalls (21).
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: October 27, 1998
    Assignee: Motorola, Inc.
    Inventors: William J. Wied, Kanchei Loa
  • Charge pump circuit and method
    Patent number: 5825640
    Abstract: A circuit and method produce a pump current (I.sub.p) at the output (31) of a charge pump (26). A switching transistor (32, 35) is coupled at a node (38, 39) to a current source transistor (33, 34) to produce the pump current at a specified magnitude in response to an input pulse (V.sub.PU, V.sub.PD). A charge is stored on a parasitic capacitance of the node. A charge conduction path (42, 43) is coupled to the node and enabled on one transition edge of the input pulse to alter the charge by routing to a discharge node (45) to reduce charge flowing to the output as an error current. The charge conduction path is disabled on the other transition edge of the input pulse to isolate the node from the output.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: October 20, 1998
    Assignee: Motorola, Inc.
    Inventors: John H. Quigley, David A. Newman