Abstract: An object of the present invention is to contribute to increase of storage capacity of a memory. A non-volatile memory having a cell applying to multi-bit data by double layered floating gate architecture. The memory has a storage cell transistor which comprises source 2 and drain 3 being formed in a semiconductor substrate 1 distantly from each other. The storage cell transistor, furthermore comprises a single first floating gate 4A being laid between the source and drain above the semiconductor substrate, and a plurality of second floating gates 4B.sub.1 -4B.sub.n which are distant from each other and face the first floating gate. Since the second floating gates respectively store carrier corresponding to data bits and the first floating gate determines a threshold value of drain current in accordance with sum amount of carrier stored in all of the second floating gates, two or more bits data can be saved per one storage cell.

Abstract: An integrated circuit assembly (16) embodied as flip-chip is encased in a plastic card (12) to form a smart card assembly (10). The flip-chip assembly has a substrate (20) with plated pads, and a semiconductor die (30) with contacts (32) to be connected to the plated pads on the substrate. An adhesive (38) is applied at selected locations less than an entire surface area between the substrate and the die for maintaining a fixed positional relationship between the substrate and the die. The selected locations, typically dots or a bead inside or around the perimeter of the die, have detrimental stress induced by differences in coefficients of thermal expansion between the die and the substrate before the contacts of the die are connected to the plated pads of the substrate during a reflow or cure process.

Abstract: A method for remote system monitoring which comprises two computer systems which operate independently but which are linked in such a way that they can exchange electronic mail with each other. An electronic mail message is sent between the computer systems which activates a monitoring program on the remote computer system. The monitoring program generates a status report which is returned to the monitoring computer by means of a second electronic mail message.

Abstract: A computer implemented method provides for simulation standard cells from an integrated circuit design in parallel on a distributed simulation system. The integrated circuit design (10) is divided into a plurality of standard cells (12-18). Characterization parameters such as temperature, process, supply voltage, edge rate and capacitive load are individually assigned (34) to each one of the standard cells. A first one (12) of the standard cells is scheduled (36) and dispatched (38) for simulation in a first computer workstation (22) on the distributed simulation system (20). A second one (14) of the standard cells is scheduled and dispatch for execution in a second computer workstation (24) on the distributed simulation system during the simulation of the first standard cell. The results of the first and second simulations are stored (40) upon completion of the respective simulation tasks.

Abstract: An integrated circuit (22) processes baseband video signals to produce a picture-in-picture (PIP) channel for a video monitor (26). A discretionary control circuit (64) on the integrated circuit monitors parental discretionary control data on a predetermined horizontal line (21) of the baseband video signal. The discretionary control data is a value that represents the amount and degree of sex and violence in the presently viewed program. The parent or responsible party stores a threshold value in a television control circuit. The discretionary control circuit compares the discretionary control data to the threshold value. If the discretionary control data is less than the selectable threshold, then the PIP channel is displayed. If the discretionary control data is greater than the selectable threshold, then the PIP channel is blanked.

Abstract: A circuit 100 for determining the polarity of an input sequence of pulses 200 or 300 applied to input 102 by digitally determining the polarity of a predetermined number of pulses of the input sequence of pulses using the digital polarity determinator 130 and, dependent on the output of the digital polarity determinator 130, routing the input sequence of pulses by the polarity switch 120 to the output 135 when the polarity of the input sequence of pulses is a predetermined polarity, and routing the input sequence of pulses to the output 135 via the inverter 125 when the polarity of the input sequence of pulses is not the predetermined polarity, thereby providing an output sequence of pulses having only the predetermined polarity.

Abstract: A memory 220 comprising address register 305, control register 310, status register 315, message register 320, and receive address register information register 325, are coupled to a decoder 240 and a microcontroller 250 via a parallel bus 235 and 230. The microcontroller 250 controlling the operation of the decoder 240 to receive and decode a selective call signal from the receiver circuitry 102, the microcontroller 250 communicating with the decoder 240 by storing and retrieving information in the registers in the memory 220. The decoder 240 communicating with the microcontroller 240 by storing and retrieving information in the registers in the memory 220.

Abstract: A telecommunications device (10) includes an input terminal (12,13) for coupling to an input line of a telecommunications network. A detection arrangement (17, 18, 23) is coupled to the input terminal (12,13) for providing an output voltage in response to a voltage on the input line exceeding a threshold level. An output terminal (21) is coupled to receive the output voltage from the detection arrangement (17, 18). The detection arrangement (17, 18) includes a control arrangement (17) for setting the threshold level in response to a received control signal (19).

Abstract: Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0.degree. to 70.degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current.

Abstract: A method of electrically modeling a semiconductor package is provided. The method reduces computation time for mutual inductance calculations between interconnect lines of the semiconductor package. Only interconnect within a predetermined distance of an interconnect line being modeled is calculated for mutual inductance. The predetermined distance is selected such that any interconnect line greater than the predetermined distance away from the interconnect line being modeled produces a negligible or small mutual inductance. This greatly reduces the number of calculations for semiconductor packages having a large number of interconnect lines. Each interconnect line modeled is broken into segments for calculating mutual inductance. An algorithm is used that calculates the mutual inductance between a pair of arbitrarily oriented straight line metal segments.

Abstract: A modification circuit (30) is thermally coupled to and electrically isolated from a circuit element (20) of a utilization circuit (10). During modification, current pulses are passed through an isolation circuit (40) to the modification circuit which heats the circuit element, e.g., a resistor, of the utilization circuit substantially above the normal operating temperature range of the element, thereby modifying the electrical characteristics of the resistor and therefore those of the utilization circuit to which it is connected. During normal operation of the utilization circuit the circuit element of the utilization circuit is electrically isolated from the modification circuit.

Abstract: A leadframe (10) architecture provides placement of multiple optocoupler pair devices (45, 50) in a minimum size footprint package. A detector flag (20) and LED flag (12) are placed on a common centerline (26) within the footprint. A critical length is determined for packaging factors lying along the centerline. The angle (28) formed between the centerline and the longitudinal axis (24) controls the optocoupler pair fit within the package. The angle (28) is calculated by taking the arc-sine function of the critical length divided by the footprint width.

Abstract: A voltage source device for low-voltage operation which sources a desired voltage while minimizing variations in output voltage due to changes in temperature. The voltage source device includes a current source circuit having a temperature characteristic of (1/T)-a and a compensation circuit having a temperature characteristic that includes a term of -1/T, which compensates for the temperature characteristic of the current source circuit. The voltage source device also includes a voltage conversion circuit for converting the power supply current provided by the current source circuit into a power supply voltage and outputting it externally.

Abstract: A data transmitter (12) transmits parallel data as light pulses over multiple optical channels (14). A data receiver (16) converts the light pulses back to a voltage level and compares the voltage level to a reference capacitor voltage (42). The capacitor voltage should maintain a mid-range value for proper noise margin in detecting logic ones and logic zeroes. Any long series of consecutive logic ones or zeroes causes the capacitor voltage to charge or discharge toward the same level as the data voltage, which causes data errors. To prevent the data errors, the data is encoded (18) by inverting certain bits to break up the long series of consecutive logic states. The encoding information is transmitted as a transmitted clock to the data receiver over another fiber optic channel. The decoding information is retrieved (20) so that the encoded data can be converted back to proper logic states.

Abstract: A method of generating power vectors to calculate power dissipation for a circuit cell is provided. The method involves formulating the Boolean equations (30) that describe the logical operation for a circuit cell (10). Primitive power vectors that cause an output to transition are generated (32) using Boolean difference functions. Internal power vectors that cause an internal node to transition without transitioning the output are generated (34) using Boolean difference functions. Static power vectors with all possible steady state inputs are also generated (36). The power vectors are minimized (38) to eliminate redundant vectors. The resulting power vectors can be used in a circuit simulation in evaluating (40) the power dissipation of a designed logic circuit.

Abstract: A method for maintaining alignment of a stack of spring washers mounted on a shaft. A retainer (44) is provided with an opening (41) for mounting on a shaft (49), a planar surface (42) for contacting outer contact edge (46) of spring washer (47) and a retaining lip (43) for limiting the lateral movement of spring washer (47).

Abstract: A current limit circuit (10) uses a reference current (28) with zero temperature coefficient. A feedback loop (18, 26, 22) maintains substantially equal V.sub.GS for first (22) and second (24) transistors. The reference current sets the current through the first transistor which therefore limits the current in the second transistor. The second transistor is a power device that supplies current to a squib detonation device (38) in automotive air bag application.

Abstract: An electro-static discharge (ESD) protection circuitry 100 with a gate-capacitor-coupled (GCC) device 120 or 125 and a silicon controlled rectifier (SCR) 130 or 135 coupled to an output 101 of an output device 116 or 117 in a sub micron metal oxide semiconductor circuit is disclosed. The GCC device 120 or 125 has a lower ESD breakdown voltage than the output device 116 or 117, hence, the GCC device 120 or 125 breaks down and causes the SCR 130 or 135 to breakdown when a destructive ESD voltage impinges on the out put 101 of the output device 116 or 117. The SCR 130 or 135 upon breaking down, discharges the destructive ESD to the power supply bus VDD or VSS.

Abstract: A complimentary switched amplifier transceiver (10) is provided which offers performance advantages and reduces system complexity over conventional half-duplex transceivers by using complimentary switched amplifiers for eliminating switches. Power output to a channel transition (31) from a transmit amplifier (26) is not degraded by a switch insertion loss in a transmit mode. Receiver noise figure is not degraded due to the switch insertion loss from the channel transition (31) to a receive amplifier (27). Switch devices and their associated control lines are eliminated, reducing circuit complexity for complimentary switched amplifier circuits such as a combined amplifier switch (12) and a first bi-directional amplifier (22).

Abstract: A method is described for maintaining a constant Q in a voltage controlled oscillator (VCO) which is tuned over a broad frequency band. A tank circuit (111) sets a center frequency of an oscillator circuit (112). A variable reactance circuit (113) provides a variable effective reactance across the tank circuit (111) corresponding to an applied tuning voltage (117) for tuning the VCO. Resistive currents from the variable reactance circuit are rectified by a rectification circuit (120). A comparator produces a Q control voltage corresponding to the rectified resistive currents and a reference current Iref at a terminal (126) which is coupled to a variable resistance circuit (122) for supplying differential resistive currents to the tank circuit (111) which offset the resistive currents from the variable reactance circuit, thereby maintaining a constant Q in the VCO.