Abstract: Innovative systems and methods for advantageous use of a new isolated power converter topology, in which transformer isolation is provided by a very simple DC-DC converter operated in open-loop mode (with each switch running at a constant duty cycle of approximately 50%, to achieve an effective duty cycle of approximately 100%), and feedback or modulation is instead applied to a preconverter stage which also does power factor corrections. Since the isolation stage is operated at a constant duty cycle, distortion can be minimized and its efficiency can be fully optimized, with a simple circuit and small component count. Unlike a flyback converter, only a very small inductance is required. A simple control architecture is used with current control loop. The disclosed circuit tightly clamps the voltages on the switch and on the transformer, with no ringing nor overshoot.

Abstract: A universal battery pack which contains an integral transformerless DC--DC switching power converter, with no DC connection between the battery and the power terminals. This provides inherent protection against overcurrent, and permits smaller fuse sizes to be used for a given current rating.

Abstract: A portable computer docking system wherein the angle of the slot which receives the portable computer can be adjusted for ergonomic optimization, while keeping the docking unit as a whole stationary in its mounted location.

Abstract: A system and method to reduce power consumption in a portable computer system while allowing the CDROM drive to continue playing audio CDs. When the system enters a suspend mode, the status of the CDROM drive is checked, and if it is playing an audio CD, it remains powered, otherwise power to the CDROM drive is also suspended. The system recognizes when the audio CD is finished playing and then places the CDROM drive into the suspend mode.

Abstract: A 3D rendering accelerator, in which the hardware texturing capability is also used to provide enhanced 2D rendering. Texturing units, when operating in a 2D mode, are available for use for storing icons and characters locally to avoid the expense of doing a lookup from the host system. Texturing units are also used as storage for pattern data for performing a tiled fill of a graphical object and for defining arbitrarily large stipple patterns. Color index dither patterns may also be stored in the texture units to avoid the necessity of doing a texture download from the host system.

Abstract: A portable computer docking station in which the computer is inserted vertically into a vertical slot. An additional slot receives modular accessories (such as a CD drive, floppy disk drive, or extra battery) to be inserted. Connectors in the vertical slot provide power to the computer, and provide connection to external display and user input devices, and also provide electrical connection from the computer to whichever module is in the additional slot, and also provides charging if the additional module is a battery.

Abstract: An innovative method of making pinatas utilizes pre-cut and scored cardstock designed with tab and slot closures. Once the shapes are folded and secured, the pinatas can be decorated using traditional or innovative methods. By designing the tab/slot closure of the body on the bottom of the pinata, the enclosed treats may be released in a non-destructive manner.

Abstract: A universal battery pack which includes an integral power converter and a dynamically adjustable output voltage. The default output voltage is set by an optional resistor connection, which shifts the voltage-dividing ratio into the error amplifier. In a multiple-battery configuration, the output voltages of the separate battery modules are preferably set to slightly different values. Thus the battery module with the highest output voltage setting will be completely exhausted first. This results in automatic battery switchover, without requiring any control algorithm or logic for execution of the switchover.

Abstract: The integrated circuit comprises a central processing unit, a program memory containing a program of instructions connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory, the instructions being carried out by the central processing unit, and at least one data memory connected to the central processing unit by an address bus, a data bus and lines giving control signals for read and write access to this memory. The circuit comprises breaking means enabling the defining of a combination of conditions pertaining to the values present on two of the buses of the memories and to the values of the control signals for access to at least one of these memories, and halting the performance of the instructions if these conditions are verified. The disclosed device is especially valuable for testing an application program of the integrated circuit.

Abstract: Converter topologies in which two separate switching transistors and two capacitors are used on the input side. Preferably the two transistors are switched alternately, to alternately pull down different nodes in an inductor-capacitor chain. Two capacitors are interposed in series between an input inductor on the input and a transformer primary winding. Preferably the two transistors are connected with their parasitic diodes in opposite senses, so that one can source current from a first node to ground when off, and the other can sink current from a second node to ground when off.

Abstract: A circuit for the filtering of a pulse signal comprises means to detect an output pulse upon the detection of an input pulse, the shape of this output pulse being based on elementary delays obtained by the charging and discharging of capacitors. During the generation of the output pulse, no new input pulse can be taken into account.

Abstract: A graphics processing system with a message-passing architecture, in which the rasterizer can be bypassed by a particular type of message from the host. This permits rasterization to be slaved to the host downloads and bitmasks, so that images and patterns can be applied to lines and polygons, rather than just rectangles as is the case for prior art.

Abstract: The speed of a capacitive cell RAAM used for storing an optical image as electric charge is greatly enhanced by presampling the serial analog input signal on two rows or lines of presampling capacitors, each composed of the same number of capacitors as the number of columns of the capacitive cell RAAM and by "writing" in a parallel mode the selected row of said memory. The values stored in the capacitors of one of said two presampling rows are transferred (written) in the corresponding cells of the selected row of the memory while presampling continues on the other row of presampling capacitors.

Abstract: A graphics subsystem in which a very fast clear operation is performed without the need to address each pixel, and without using memories which include a hardware fast-clear capability. This is implemented by using a reference frame counter: the window is divided up into n regions, where n is the range of the frame counter (i.e. n=2.sup.p, where p is the number of bits in the frame counter). Every time the application issues a clear command, the reference frame counter is incremented (and allowed to roll over if it exceeds its maximum value), and only the n.sup.th region is cleared. The clear updates the depth and/or stencil buffers to the new values and the frame count buffer with the reference value. This region is much smaller than the full region the application thinks it is clearing, so takes less time and hence gives the speed increase. When the local buffer is subsequently read and the frame count is found to be the same as the reference frame count, the local buffer data is used directly.

Abstract: The preferred embodiment discloses a pipelined graphics processor in which the sequence can be dynamically reconfigured (e.g. between primitives) in a rendering sequence. The pipeline sequence can be configured for compliance with specifications such as OpenGL, but may also be optimized by reconfiguring the pipeline sequence to eliminate unnecessary processing. In a preferred embodiment, pixel elimination sequences such as depth and stencil tests are performed before texturing calculations are performed, so that unneeded pixel data is discarded before said texturing calculations are performed.

Abstract: A flip-flop of the D type capable of loading data asynchronously and comprising two latches, a master and a slave one, connected in series with each other, is characterized in that each of these comprises an interface and selection circuit for input signals transferable in either the synchronous or the asynchronous manner, and a logic gate circuit which is input such signals and, in an asynchronous manner, control signals effective to establish the latch own states.

Abstract: In a computer having switch-mode power converter, a pulse transformer circuit drives the converter's transistor switch in response to pulses from a switch control pulse source. A primary capacitor is connected in series with the switch control pulse source and the transformer's primary winding. At the leading edge of a switch control pulse, the primary capacitor causes a positive voltage spike to appear across the primary winding and hence a positive voltage spike to be induced across the transformer's secondary winding. At the trailing edge of the switch control pulse, the primary capacitor causes a negative voltage spike to appear across the primary winding and hence a negative voltage spike to be induced across the transformer's secondary winding.

Abstract: A method for the parallel programming of memory words in electrically programmable non-volatile semiconductor memory devices comprising at least one matrix of floating gate memory cells with corresponding drain terminals heading columns or bit lines of the matrix and supplied during the programming stage with a drain voltage which is boosted with respect to a supply voltage (Vcc). During the parallel programming stage the supply voltage is used as a drain voltage. Switching is provided between the supply using the drain voltage or the supply voltage during the transient between single word programming and parallel programming.