Abstract: A structure of electronic devices integrated in a semiconductor substrate with a first type of conductivity comprising at least a first HV transistor and at least a second LV transistor, each having a corresponding gate region. Said first HV transistor has lightly doped drain and source regions with a second type of conductivity, and said second LV transistor has respective drain and source regions with the second type of conductivity, each including a lightly doped portion adjacent to the respective gate region and a second portion which is more heavily doped and comprises a silicide layer.

Abstract: Embodiments of the invention provide a circuit for generating a trapezoidal signal with controlled wavefronts, particularly for a converter for a satellite receiver, comprising a first oscillator suitable to generate a square-wave signal and a second oscillator which is cascade-connected to the first oscillator, wherein the second oscillator is synchronized with the first oscillator and is suitable to generate a voltage signal which is amplitude-modulated with a trapezoidal modulating signal.

Abstract: A process forms a structure incorporating at least one circuitry transistor and at least one non-volatile memory cell of the EEPROM type with two self-aligned polysilicon levels having a storage transistor and an associated selection transistor in a substrate of semiconductor material including field oxide regions bounding active area regions. The process comprises the steps of, in the active area regions, forming a gate oxide layer and defining a tunnel oxide region included in the gate oxide layer; depositing and partly defining a first polysilicon layer; forming an interpoly dielectric layer and removing the interpoly dielectric layer at least at the circuitry transistor; depositing a second polysilicon layer; selectively etching away, through a first mask, at least the second polysilicon layer at the cell, and the first and second polysilicon layers at the circuitry transistor; and selectively etching away, through a second mask, the interpoly dielectric layer and the first polysilicon layer at the cell.

Abstract: An ESD protection network protects a CMOS circuit structure integrated in a semiconductor substrate. The circuit structure includes discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply having a respective primary ground, and from at least one secondary voltage supply having a respective secondary ground. This network includes a first ESD protection element for an input stage of the circuit structure; a second ESD protection element for an output stage of the circuit structure, the first and second protection elements having an input/output pad of the integrated circuit structure in common; a first ESD protection element between the primary supply and the primary ground; and a second ESD protection element between the secondary supply and the secondary ground.

Abstract: Presented is a low-drop type of voltage regulator formed with BiCMOS/CMOS technology. The regulator includes an input terminal that receives a stable voltage reference connected to one input of an operational amplifier through a switch controlled by a power-on enable signal. A supply voltage reference powers the operational amplifier. The regulator includes an output transistor connected to an output of the amplifier to generate a regulated voltage value to be fed back to the amplifier input. A second transistor is connected in series between the output transistor and the supply voltage reference. The regulator uses a control circuit portion connected between the control terminal of the second transistor and the supply voltage reference to prevent the breakdown of the output transistor from occurring.

Abstract: A microactuator comprises an outer stator and an inner rotor electrostatically coupled to a stator. The rotor comprises a suspended mass with a substantially circular shape, and a plurality of mobile arms extending radially towards the exterior, starting from the suspended mass. The stator has a plurality of pairs of fixed arms extending radially to the suspended mass, a respective mobile arm being arranged between each pair of fixed arms. The fixed arms are divided into fixed drive arms connected to a drive stage for actuating the microactuator, and into fixed measure arms connected to a measure stage, and define a capacitive uncoupling structure.

Abstract: The driving capability of a selection transistor is increased by an N-type implant at the source and drain regions of the selection transistor itself. This implant is conveniently made at the end of the self-aligned etching, using the same self-aligned etching mask defining the control gate regions and the floating gate regions of memory elements, keeping the circuitry area covered by a circuitry mask.

Abstract: Presented is a circuit device for driving an a.c. electric load, incorporating a rectifying bridge that has a first input connected to one terminal of the electric load and a second input connected to an outlet of an a.c. main supply. The rectifying bridge has output terminals connected to a power switch which is controlled by an electric signal. The circuit device has a circuit loop-back link connected in parallel to the electric load, and a second circuit loop-back link connected in parallel to the electric load. The first and second links are alternately activated by the positive and negative half-waves of the main supply when the switch is in its “off” state.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Polyl mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas . Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.

Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.

Abstract: Presented is a voltage regulating circuit for a capacitive load, which is connected between first and second terminals of a supply voltage generator. The regulating circuit has an input terminal and an output terminal, and includes an operational amplifier having an inverting input terminal connected to the input terminal of the regulating circuit and a non-inverting input terminal connected to an intermediate node of a voltage divider. The voltage divider is connected between an output node, which is connected to the output terminal of the regulating circuit, and the second terminal of the supply voltage generator. The operational amplifier has an output terminal connected, for driving a first field-effect transistor, between the output node and the first terminal of the supply voltage generator. The output terminal of the operational amplifier is also connected to the output node through a compensation network.

Abstract: A method drives a three-phase motor having first, second, and third coils. The method electrically connects the first coil to a first voltage reference and the second coil to a second voltage reference while leaving the other coil floating during a first driving phase. During a second driving phase, the first coil is electrically connected to the first voltage reference and the third coil is electrically connected to the second voltage reference while the second coil is left floating. During a transition phase that immediately follows the fast driving phase and immediately precedes the second driving phase, the second coil is electrically connected alternately to the first and second voltage references. By alternately connecting the second coil to the first second voltage references and during the transition phase, the method causes the current through the second coil to reduce to zero at a slower rate than prior methods.

Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal. First and second field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node which is coupled to the first and second voltage generators through a bias circuit block effective to bias the node to the higher of the instant voltages generated by the first and second generators.

Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: The invention relates to a method and a device for recognizing and warning of the level of fullness of a waste container in a suction system driven by a motor and provided with an internal chamber kept under suction pressure and comprising the waste container. The method foresees a measurement of the difference of pressure between the internal chamber and the environment outside the vacuum cleaner and an elaboration of such measurement according to a set of rules in fuzzy logic for producing an electric warning signal corresponding to the filling level of the waste container.

Abstract: A content addressable memory (CAM) protection circuit includes a memory cell having a read terminal for reading contents of the memory cell; a pass transistor coupled to the read terminal; and a latch having a first inverter with an input terminal and an output terminal coupled to the read terminal by the pass transistor and a second inverter with input and output terminals respectively coupled to the output and input terminals of the first inverter. The first inverter includes a pull-down transistor coupled between the output terminal of the first inverter and a first voltage reference and having a control terminal coupled to the input terminal of the latch and a pull-up transistor coupled between the output terminal of the first inverter and a second voltage reference and having a control terminal coupled to the input terminal of the latch.

Abstract: The charge injection circuit of this invention comprises at least one pair of floating gate MOS transistors having source and drain terminals which are coupled together and to an injection node, and at least one corresponding pair of generators of substantially step-like voltage signals having an initial value and a final value, and having outputs respectively coupled to the control terminals of said transistors. The signal generators are such that the initial value of a first of the signals is substantially the equal of the final value of a second of the signals, and that the final value of the first signal is substantially the equal of the initial value of the second signal.

Abstract: A method of identifying fingerprints, the method including the steps of: acquiring a test image formed by a number of test points characterized by different grey levels defining a test surface; determining significant points in the test image; and verifying the similarity between regions surrounding the significant points and corresponding regions of a reference image whose points present different grey levels defining a reference surface. The similarity between the regions is verified by computing the integral norm of portions of the test and reference surfaces; and the integral norm is computed using flash cells programmed with a threshold value correlated to the value of the grey levels in the reference region, by biasing the flash cells with a voltage value correlated to the grey level in the test region, and measuring the charge flowing through the flash cells.