Abstract: The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: A process for manufacturing electronic semiconductor integrated electronic memory devices having virtual ground and including at least a matrix of floating gate memory cells formed on a semiconductor substrate with a plurality of continuous bit lines extending across the substrate as discrete parallel strips begins with forming an oxide layer over the matrix region. Then, the semiconductor throughout is deposited with a stack structure which includes a first conductor layer, a first dielectric layer, and second conductor layer. Next, a second dielectric layer is formed. Floating gate regions are defined by photolithography using a mask of “POLY1 along a first predetermined direction”, and associated etching, to define, in the stack structure, a plurality of parallel openings. These openings are implanted to confer a predetermined conductivity on the bit line regions. Next, the parallel openings are filled with a photo-sensitive material to protect the matrix bit lines.

Abstract: The cells of the stacked type each comprise a MOS transistor formed in an active region of a substrate of semiconductor material and a capacitor formed above the active region; each MOS transistor has a first and a second conductive region and a control electrode and each capacitor has a first and a second plate separated by a dielectric region material, for example, ferroelectric one. The first conductive region of each MOS transistor is connected to the first plate of a respective capacitor, the second conductive region of each MOS transistor is connected to a respective bit line, the control electrode of each MOS transistor is connected to a respective word line, the second plate of each capacitor is connected to a respective plate line. The plate lines run perpendicular to the bit line and parallel to the word lines. At least two cells adjacent in a parallel direction to the bit lines share the same dielectric region material.

Abstract: A non-volatile memory device is organized with memory cells that are arranged by row and by column. The memory device includes a sector of matrix cells, row decoders and column decoders suitable to decode address signals and to activate respectively the rows or said columns, at least a sector of redundancy cells such that it is possible to substitute a row of the sector of matrix cells with a row of the sector of redundancy cells. The non-volatile memory device comprises a local column decoder for the matrix sector and a local column decoder for the redundancy sector. The local column decoders are controlled by external signals so that the row of the redundancy sector is activated simultaneously with the row of the matrix sector.

Abstract: A method and apparatus to dynamically modify the internal compensation of a low drop out linear voltage regulator is presented. The process involves using zero mobile compensation; when the output pole of the voltage regulator moves, a compensating zero is moved toward higher frequencies. This compensation zero is used to compensate the effect of a second pole in the loop gain. The circuit includes an input stage having an error amplifier. The error amplifier includes a differential stage output coupled to an output terminal of the buffer stage. An output stage of the circuit includes an output transistor having a conduction terminal connected to an output terminal of the voltage regulator, and having a control terminal coupled to the output terminal of the buffer stage. Additionally, a variable compensation network is connected between the differential stage output and a voltage reference. This variable compensation network can include an RC circuit having a resistive transistor.

Abstract: The sensing circuits comparing the current flowing in the cell with a plurality of reference currents are not identical to each other but differently amplify the compared currents. In particular, the sensing circuit associated with the lowest reference current amplifies the cell current more than the other sensing circuits and to the respective reference current. The current dynamics is thereby increased and it is possible to keep the reading voltage low, since the inherent characteristic of the lowest reference current may be very close to or directly superimposed on that of the immediately preceding memory cell current distribution, retaining the possibility of discriminating between the different logic levels.

Abstract: Presented is a process for manufacturing virtual ground electronic memory devices integrated in a semiconductor having a conductivity of a first type and having at least one matrix of floating gate memory cells. In the matrix there are a number of continuous bit lines extending across the substrate as discrete parallel strips, and a number of word lines extending in a transverse direction to the bit lines. The method begins by forming gate regions of the memory cells to produce a number of continuous strips seperated by parallel openings. Then, a dopant is implanted to form, within the parallel openings, the bit lines with conductivity of a second type. Spacers are formed on sidewalls of the gate regions. Then a first layer of a transition metal is deposited into said parallel openings, and the transition metal layer is subjected to a thermal treatment for reacting it with semiconductor substract and forming a silicide layer over the bit lines.

Abstract: An active precision termination of the type incorporated in a voltage regulator for feeding the lines of an external bus is presented. Each termination includes a matching impedance connected in series to a switch formed by a MOS transistor, including a cell formed by a plurality of circuit branches provided in parallel and coupled to a unique output terminal. Each branch includes an input coupled to the series of the impedance and of the switch and receiving a control voltage signal. The body terminal of each MOS transistor receives a corresponding control signal via an inverter, whereas the control terminal of each MOS transistor receives a corresponding control voltage signal.

Abstract: A device controller controls access to a device, such as a television, having a power input for receiving power and a data input for receiving control data. When in standby mode, the device controller disconnects the device from a power source, such as the AC mains of the building in which the device is situated. As a result, in standby mode only the device controller is powered, which uses much less power than prior art devices in standby mode. The device controller includes an input device structured to provide control data based on control instructions received from a user, a power switch coupled between a power source and the device power input, and a data coupler coupled to the device data input and structured to convert electrical data into non-electrical data and back to the electrical data for delivery to the device data input.

Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

Abstract: A voltage level shifter and an associated level shifting method for shifting from a low voltage input signal to a high voltage output signal are discussed. The level shifter includes a voltage shifting stage having first and second control input nodes and an output node at which the output signal is produced based on control signals received at the control input nodes. The level shifter also includes first and second input inverters coupled in series between the input node and the first control input node; and a third input inverter coupled between the input node and the second control input node. The second inverter can include complementary first and second transistors each with control terminals coupled to an output of the first inverter. The first transistor has a first terminal coupled to the input node and is structured to pass the input signal to the first control input node based on a logic value of a signal output by the first inverter.

Abstract: The high-voltage bidirectional switch includes a controlled transistor having a first terminal and a second terminal set, respectively, at a first potential and at a second potential. The controlled transistor moreover includes a control terminal connected to a control block, which is in turn connected to a precharge block The controlled transistor has its bulk region connected to a biasing block which is in turn connected both to the precharge block and to the second terminal of the controlled transistor. The control block and the biasing block are moreover connected to a signal-generator block connected to a control unit.

Abstract: A voltage regulator for memory circuits has a differential stage having a non-inverting input terminal receiving a control voltage independent of the temperature; an inverting input terminal connected to a ground voltage reference; a feed terminal connected to a booster circuit adapted for producing a boosted voltage; and an output terminal connected to an output terminal of the voltage regulator, for producing an output voltage reference starting from the comparison of input voltages. The voltage regulator further comprises a connecting transistor inserted between the feed terminal and the output terminal of the differential stage, the connecting transistor being source follower having a control terminal connected to the output terminal of the differential stage, as well as a source terminal connected to the output terminal of the voltage regulator, in such a way as to self-limit the transition of the voltage on the output terminal.

Abstract: In a CMOS process for making dual gate transistors with silicide, high-voltage transistors with drain extensions are produced by first defining on a semiconductor substrate, active areas for low-voltage and high-voltage transistors. A gate oxide layer and a layer of polysilicon is deposited over the substrate, which is masked and etched to produce gates for the transistors. A dielectric layer is deposited to produce spacers to the sides of the transistor gate regions, then a mask partially shields the dielectric layer over the junctions of the high-voltage transistors while the spacers are being formed. Finally, the substrate is doped in the gate and active areas of the high-voltage transistor, and in the gate and active areas of the low-voltage transistor, except those areas that are blocked by the spacers.

Abstract: An electronic level shifter device having very low power consumption includes a first voltage reference from a power supply and a second voltage reference from a ground. The shifter device includes a circuit portion with a differential cell having an output terminal and at least a first and a second input terminal. On the output terminal is a level translated signal with respect to a signal present on one of said input terminals. The device further comprises an additional circuit portion connected to a node of the differential cell and comprising at least a pull-down component inserted between said node and the second voltage reference. The pull-down component can be a MOS transistor having its conduction terminals connected between said node and the second voltage reference and its gate terminal connected to the first voltage reference of power supply by means of a series of transistors.

Abstract: An electronic memory device organized into sections which are in turn divided into blocks formed of cells and their associated decoding and addressing circuits, the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions which are interconnected by parallel continuous conduction lines referred to as the bit lines. In the present invention, at least one interruption is provided in each bit line near a contact region by inserting a controlled switch which functions as a block selector. Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches of the cascade connected blocks.

Abstract: A ROM including columns of memory cells connected by columns to respective bit lines; a reference bit line; charge transistors controllable by a common charge line and respectively connecting the bit lines and the reference bit line to a high supply potential. The reference bit line is associated with a column of unprogrammed cells, and the memory includes means for activating the charge line before activation of a word line, the duration between the activation of the charge line and the activation of the word line, and the features of the charge transistors, being chosen so that the level variation of the bit lines is low as compared to the level of the high supply potential.

Abstract: A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.