Patents Represented by Attorney Robert J. Depke
  • Patent number: 8102336
    Abstract: A pixel has an outer region extending linearly along a boundary with an adjacent pixel and an inner region extending along the inner side of the outer region. Wiring lines are arranged across the outer region and the inner region. An outer uneven zone is formed along the outer region and on a substrate due to level differences resulting from the presence of the wiring lines. Similarly, an inner uneven zone is formed along the inner region and on the substrate due to level differences resulting from the presence of the wiring lines. A pattern of a conductor film of which the wiring lines are made is formed properly such that recessed portions of the outer uneven zone are located directly behind their corresponding raised portions of the inner uneven zone, as viewed from inside the pixel.
    Type: Grant
    Filed: March 15, 2008
    Date of Patent: January 24, 2012
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Tetsuro Yamamoto
  • Patent number: 6925774
    Abstract: An automated solid pharmaceutical product packaging machine includes a plurality of temporary storage members for receiving a plurality of solid pharmaceutical products in a plurality of cavities. The use of the temporary storage cavities enables the machine to process several prescriptions simultaneously. Advantageously, at least one of the temporary storage members is capable of being automatically displaced in a vertical direction in order to increase the capacity of the overall filling system for processing a greater number of solid pharmaceutical products while minimizing the overall footprint of the device.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: August 9, 2005
    Assignee: MTS Medication Technologies, Inc.
    Inventor: Raymond Peterson
  • Patent number: 6836274
    Abstract: A method and apparatus of displaying an Electronic Programming Guide (EPG). In one embodiment, an EPG is displayed in a three dimensional virtual mesh, in which independent objects representing television programs are situated. The simplified nature of the three dimensional EPG reduces the amount of processing necessary to display it. In addition, the virtual mesh may be displayed isometrically, so that hardware requirements are further reduced and it may be possible to use a software only three dimensional graphics pipeline. If a user has a set top box (STB) with a hardware accelerated graphics pipeline, the EPG may be displayed in a full three dimensional perspective view. A user can navigate the mesh to find television programs that they wish to view. A user can assign values to types of television programs that they prefer, and these programs will be displayed more prominently.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: December 28, 2004
    Assignee: Eagle New Media Investments, LLC
    Inventor: Dan Kikinis
  • Patent number: 6834964
    Abstract: The present invention provides a liquid crystal projector including a plurality of liquid crystal panels, a prism for compositing the modulated plural color lights to generate a color image, top and bottom metal plates disposed above and below the prism, and an optical system for magnifying and projecting the generated color image, wherein the liquid crystal panels are directly adhered to metal hold plates, and the metal hold plates are fixed to the top and bottom metal plates such that the emergent surfaces of the liquid crystal panels face the incident surfaces of the prism. Further, a closed space is provided between the incident surfaces of the prism and the emergent surfaces of the liquid crystal panels so as to prevent air contaminants from effecting the performance of the device.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: December 28, 2004
    Assignee: Sony Corporation
    Inventors: Shizuo Nishihara, Yoshifumi Akaike, Michio Nagaya, Naoko Uno
  • Patent number: 6835292
    Abstract: A polishing method able to easily flatten unevenness formed on the surface of a film to be polished and able to efficiently polish the film flat while suppressing damage to an interlayer insulating film below the film, comprising, when polishing an object having a film such as an interconnection layer formed burying interconnection grooves formed in an insulating film of a substrate, supplying a polishing solution over the surface to be polished at least substantially parallel to the surface to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the processing solution or arranging a cathode member facing the surface and supplying an electrolytic solution containing a chelating agent between the surface and cathode member while supplying voltage between the film and the cathode member to preferentially remove by polishing the projecting portions of the film and flatten the surface by the shear stress of the electrolytic solution, and a polishin
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: December 28, 2004
    Assignee: Sony Corporation
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshiq, Takeshi Nogami
  • Patent number: 6833601
    Abstract: A semiconductor device includes a plurality of photoelectric conversion photodiodes provided on a silicon substrate, and a refractive index matching film provided on each of the photodiodes. The refractive index matching film is composed of an insulating compound layer represented by SiOxNy (0≦x and y) assuming that the molar ratio of silicon, oxygen and nitrogen of the compound layer is 1:x:y. The oxygen content of the compound layer is the lowest at the silicon interface with each photodiode and the highest in an upper portion of the compound layer, and the nitrogen content is the highest at the silicon interface with each photodiode and the lowest in the upper portion of the compound layer. Therefore, multiple reflection can be decreased to improve light receiving sensitivity, as compared with a case in which a SiN single layer and a SiO2 single layer are laminated.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: December 21, 2004
    Assignee: Sony Corporation
    Inventor: Ichiro Murakami
  • Patent number: 6833870
    Abstract: In a charge transfer device which has many two-layered transfer electrodes, 8L disposed along a charge transfer direction X above a transfer channel is driven with two-phase driving pulses supplied to the transfer electrodes of the second layer, the transfer channel below the last-stage transfer electrode disposed at the last stage of the charge transfer direction X is constructed to have three-step potential, and the potential is set to be stepwise deeper from the upstream side to the downstream side in the charge transfer direction X.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: December 21, 2004
    Assignee: Sony Corporation
    Inventor: Naoki Nishi
  • Patent number: 6833872
    Abstract: A progressive all-pixel scanning type solid-state image sensor adapted for curtailing the power consumption therein by lowering its read voltage with another advantage of reducing the pixel size. The image sensor comprises pixels arrayed to form a matrix, vertical transfer registers corresponding respectively to individual columns of the pixels, read gates formed correspondingly to the individual pixels for reading out signal charges from the pixels to the vertical transfer registers, and a means for applying phase-shifted read pulses respectively to plural kinds of read gate electrodes in the read gates.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: December 21, 2004
    Assignee: Sony Corporation
    Inventor: Shinji Nakagawa
  • Patent number: 6831357
    Abstract: A circuit substrate device composed of a circuit unit 2 and a multi-layer wiring substrate 3 in which a pattern conductor of the circuit unit 2 may be prevented from being warped or inundated. The circuit substrate device includes a circuit unit 2 having a pattern conductor formed by a thin film technique, and an insulating layer, and a multi-layer wiring substrate 3 having a connecting terminal portion 14 exposed from its major surface. The circuit unit is formed on a dummy substrate. The circuit unit is connected to the multi-layer wiring substrate 3 so that the pattern conductor is connected to the connecting terminal portion 14. The dummy substrate is then removed to give a structure comprised of the circuit unit 2 formed on the multi-layer wiring substrate 3. The pattern conductor of the circuit unit 2 is freed of warping or inundations along the direction of thickness of the circuit unit 2.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: December 14, 2004
    Assignee: Sony Corporation
    Inventors: Yuji Nishitani, Tsuyoshi Ogawa, Hiroshi Asami, Akihiko Okubora
  • Patent number: 6822306
    Abstract: The reduction in size, noise and voltage is realized in a MOS solid-state imaging device. A gate electrode in a pixel part is formed in a two-level structure. An amplifier gate of an amplifier transistor is formed in the first level while a select gate of a select transistor is formed in the second level. The both are structurally partly overlapped. With the first-level amplifier gate as self-alignment, ions are implanted for a select gate in the second level. Although the gate electrode if formed in one level as in the conventional requires a space of nearly a design rule between the amplifier gate and the select gate, the structure of the invention can eliminate such a dead space. Meanwhile, because the diffusion layer does not exist between the amplifier gate and the select gate, the diffusion layer is eliminated of sheet resistance and voltage drop.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: November 23, 2004
    Assignee: Sony Corporation
    Inventor: Keiji Mabuchi
  • Patent number: 6822714
    Abstract: An ultraviolet light responsive type liquid crystal alignment films are formed on opposing surfaces of a pair of transparent substrates constituting a liquid crystal cell. Next, the liquid crystal alignment films on the transparent substrates parallel to a reference plane are irradiated by a polarized ultraviolet ray dividedly by the pixel or by the dot so as to regulate an alignment direction of the liquid crystal. Furthermore, the transparent substrate that has been irradiated by the polarized ultraviolet at the previous step is irradiated by the polarized ultraviolet ray dividedly by the pixel or by the dot for developing a pre-tilt angle after rotating the transparent substrate on the reference plane so that the transparent substrate turns to a direction different from its direction at the previous step.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: November 23, 2004
    Assignee: Sony Corporation
    Inventor: Yoshimasa Saito
  • Patent number: 6821809
    Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: November 23, 2004
    Assignee: Sony Corporation
    Inventors: Takashi Abe, Nobuo Nakamura, Keiji Mabuchi, Tomoyuki Umeda, Hiroaki Fujita, Eiichi Funatsu, Hiroki Sato
  • Patent number: 6818960
    Abstract: A magnetic recording medium improved in spacing loss and durability is disclosed. The magnetic recording medium is composed so that a magnetic layer is formed on a non-magnetic support, further thereon a non-magnetic protective layer having projected portions formed thereon in a discrete manner according to a thickness distribution, and further thereon a lubricant layer is formed so as to produce surface projections. In other words, the projected portions are formed in a discrete manner to the non-magnetic protective layer formed on the magnetic layer, where the non-magnetic protective layer is principally intended for the purpose of rust prevention or the like for the magnetic layer. The whole portion of the non-magnetic protective layer inclusive of the projected portions is composed with the same material.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 16, 2004
    Assignee: Sony Corporation
    Inventor: Nobuyuki Nagai
  • Patent number: 6817704
    Abstract: In a liquid ejecting device having a head formed by a liquid ejecting portion or liquid ejecting portions arranged in parallel, the direction of ejected liquid is controlled for each liquid ejecting portion. In the head of the liquid ejecting device, heating resistors which are connected in series to one other in a liquid cell are arranged in parallel in a predetermined direction. The liquid ejecting device includes a main operation controller which performs control for ejecting liquid by supplying equal amounts of currents to the connected heating resistors, and a sub operation controller including a current-mirror circuit connected to a junction of heating resistors and its switching element. By using the current-mirror circuit and the switching element to allow a current to flow into or from a junction of the heating resistors, the amounts of currents supplied to the heating resistors are controlled and the direction of ejected liquid is controlled (changed).
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: November 16, 2004
    Assignee: Sony Corporation
    Inventors: Takeo Eguchi, Iwao Ushinohama, Kazuyasu Takenaka, Yuichiro Ikemoto
  • Patent number: 6819581
    Abstract: A ferroelectric-type nonvolatile semiconductor memory comprises a bit line BL1, a transistor for selection TR1, (C) a memory unit MU1 composed of memory cells that are M in number (M≧2), and (D) plate lines PL that are M in number; in which each memory cell comprises a first electrode 21, 31, a ferroelectric layer 22, 32 and a second electrode 33, 34, in the memory unit MU1, the first electrodes 21, 31 of the memory cells are in common, the ferroelectric layer 22, 32 is composed of lead titanate zirconate [Pb(Zrx,Tiy)O3], and said lead titanate zirconate has a composition that satisfies 0.6<Y/(X+Y)≦0.9.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: November 16, 2004
    Assignee: Sony Corporation
    Inventor: Yasuyuki Ito
  • Patent number: 6815745
    Abstract: When a tunnel magnetoresistive effect element having a multilayer film structure containing two ferromagnetic material layers (11, 12) and a barrier layer (13) is constructed, after one ferromagnetic material layer (11) had been deposited, a conductive layer (16), formed by adding a material of an element different from a metal material to said metal material serving as a principal component thereof, is deposited on the ferromagnetic material layer (11) and the barrier layer (13) is formed by oxidizing the conductive layer (16), whereafter the other ferromagnetic material layer (12) is deposited on the barrier layer (13). Thus, in the tunnel magnetoresistive effect type memory device, dispersion of resistance value between respective elements can be suppressed while a large TMR ratio can be obtained.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventors: Yutaka Higo, Kazuhiro Bessho, Tetsuya Mizuguchi, Tetsuya Yamamoto, Masanori Hosomi, Kazuhiro Ohba, Hiroshi Kano
  • Patent number: 6815222
    Abstract: Disclosed is a method for production of a semiconductor device having capacitive elements. The method includes steps of covering an insulating film formed on a substrate sequentially with a lower electrode film, a dielectric film, and an upper electrode film; applying a photoresist to the top of the films in laminate structure by photolithography, thereby forming a photoresist pattern to form an upper electrode; performing selective etching on the upper electrode film by using the photoresist pattern to form the upper electrode as a mask, thereby forming the upper electrode pattern; covering the upper electrode pattern with a photoresist pattern to form a dielectric pattern; and performing selective etching on the dielectric film by using the photoresist pattern to form the dielectric as a mask, thereby forming the dielectric pattern. The above-mentioned production method prevents a short circuit between the upper electrode and the lower electrode when the capacitive element is formed.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventor: Hirokazu Ejiri
  • Patent number: 6816219
    Abstract: A liquid crystal panel has a liquid crystal layer of liquid crystal molecules sealed between a pair of substrates having alignment films thereon. Each of the films includes first and second deposited layers, each of the layers being formed of an inorganic material by oblique deposition. The second layer is stacked on top of the first layer such that the deposited molecules of the first layer are aligned substantially perpendicular to the orientation of the deposited molecules of the second layer. The first layer is formed by oblique deposition at an oblique angle of about 60° relative to the normal of the substrate surface to align the liquid crystal molecules perpendicular to the deposited molecules. The second layer is formed by oblique deposition at an oblique angle of about 85° relative to the normal of the substrate surface to align the liquid crystal molecules parallel to the deposited molecules.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventors: Makoto Akagi, Tomoki Kurata, Hisashi Kadota
  • Patent number: 6812569
    Abstract: A semiconductor device able to maintain a bonding state between a bump and an electrode and having high reliability even under thermal stress, wherein a sealing resin is interposed to bond the electrodes and bumps between a wiring board formed with a plurality of electrodes and an IC chip formed with a plurality of bumps, the bumps being formed under the condition that the following formula is satisfied. 100<((&PHgr;A×F)/H)<125 where &PHgr;A represents the top diameter of a bump bonded with an electrode, H the height of a bump projecting from the IC chip and bonded with an electrode, and F the linear thermal expansion coefficient of the sealing resin.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: November 2, 2004
    Assignee: Sony Corporation
    Inventors: Satoshi Iwatsu, Noriyuki Honda
  • Patent number: 6808617
    Abstract: A polishing method and polishing apparatus able to easily flatten an initial unevenness with an excellent efficiency of removal of excess copper film and suppress damage to a lower interlayer insulation film, and a plating method and plating apparatus able to deposit a flat copper film. The polishing method comprises the steps of measuring thickness equivalent data of a film on a wafer, making a cathode member smaller than the surface face a region thereof, interposing an electrolytic solution between the surface and the cathode member, applying a voltage using the cathode member as a cathode and the film an anode, performing electrolytic polishing by electrolytic elution or anodic oxidation and chelation and removal of a chelate film in the same region preferentially from projecting portions of the film until removing the target amount of film obtained from the thickness equivalent data, and repeating steps of moving the cathode member to another region to flattening the regions over the entire surface.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: October 26, 2004
    Assignee: Sony Corporation
    Inventors: Shuzo Sato, Yuji Segawa, Akira Yoshio, Takeshi Nogami