Abstract: A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

Abstract: The present invention provides SOI material which includes a top Si-containing layer which has regions of different thickness as well as a method of fabricating such SOI material. The inventive method includes a step of thinning predetermined regions of the top Si-containing layer by masked oxidation of silicon. SOI IC chips including the inventive SOI material having different types of CMOS devices build thereon as also disclosed.

Abstract: A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.

Abstract: Hybrid molds for molding a multiplicity of solder balls for use in a molten solder screening process and methods for preparing such molds are disclosed. A method for forming the multiplicity of cavities in a pyramidal shape by anisotropically etching a crystalline silicon substrate along a specific crystallographic plane is utilized to form a crystalline silicon face plate used in the present invention hybrid mold. In a preferred embodiment, a silicon face plate is bonded to a borosilicate glass backing plate by adhesive means in a method that ensures coplanarity is achieved between the top surfaces of the silicon face plate and the glass backing plate. In an alternate embodiment, an additional glass frame is used for bonding a silicon face plate to a glass backing plate, again with ensured coplanarity between the top surfaces of the silicon face plate and the glass frame. In a second alternate embodiment, a silicon face plate is encased in an extender material which may be borosilicate glass or a polymer.

Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

Abstract: A method for forming a porous dielectric material layer in an electronic structure and the structure formed are disclosed. In the method, a porous dielectric layer in a semiconductor device can be formed by first forming a non-porous dielectric layer, then partially curing, patterning by reactive ion etching, and final curing the non-porous dielectric layer at a higher temperature than the partial curing temperature to transform the non-porous dielectric material into a porous dielectric material, thus forming a dielectric material that has a low dielectric constant, i.e. smaller than 2.6. The non-porous dielectric material may be formed by embedding a thermally stable dielectric material such as methyl silsesquioxane, hydrogen silsesquioxane, benzocyclobutene or aromatic thermoset polymers with a second phase polymeric material therein such that, at the higher curing temperature, the second phase polymeric material substantially volatilizes to leave voids behind forming a void-filled dielectric material.

Abstract: A broad crystal display panel having a color filter substrate is supported by supporting nails and the middle portion of a supporting span is pressed by a loading bar. From this state, the supporting nails are removed to release the supporting, and subsequently the supporting nails are also removed to release the supporting the color filter substrate. While preventing the displacement between the color filter substrate and a TFT array substrate, the color filter substrate and the TFT array substrate can be stacked with a specified distance.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: Polishing rate selectivity is increased by providing a polyelectrolyte in the polishing slurry. The polishing selectivity of silicon oxide to silicon nitride is enhanced by using an anionic polyelectrolyte. The polishing selectivity of metals to silicon oxide, silicon nitride and/or silicon oxynitride is increased by using a cationic polyelectrolyte.

Abstract: A method in which a defective semiconductor crystal material is subjected to an amorphization step followed by a thermal treatment step is provided. The amorphization step amorphizes, partially or completely, a region, including the surface region, of a defective semiconductor crystal material. A thermal treatment step is next performed so as to recrystallize the amorphized region of the defective semiconductor crystal material. The recrystallization is achieved in the present invention by solid-phase crystal regrowth from the non-amorphized region of the defective semiconductor crystal material.

Abstract: An optical switch for routing light between two waveguides is disclosed. The switch, or router, comprises a movable waveguide, the movable waveguide having two positions, wherein in a first position the movable waveguide is interposed between the two waveguides and transmits light between the two waveguides by evanescent wave coupling, and in the other position the movable waveguide is retracted from the two waveguides and is not transmitting light between the two waveguides. Means for moving the movable waveguide between the two positions is also disclosed. The optical switches are used in M×N optical routing arrays being capable of directing light from any one of the M input ports to any one of the N output ports with additional ADD/DROP functions.

Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

Abstract: A method of substantially reducing and/or eliminating the amount of defects and/or impurities that amass at interfacial surfaces that are present in a multilayer structure is provided. Specifically, the method improves the efficiency of a forming gas anneal by providing a multilayer structure having a catalytic layer formed thereon or buried therein which allows for a significant increase in the amount of hydrogen or deuterium which can be incorporated into the structure. The method is also conducted at a low temperature (on the order of about 400° C. or less). Multilayer structures are also provided which include an annealed multilayer structure having at least one interfacial surface present therein. The at least one material interface contains a region of hydrogen or deuterium which substantially reduces defects and impurities present at the at least one interface.

Abstract: A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

Abstract: A system and method are disclosed for an optical backplane in an electronic processor that comprises of a plurality of processing units. The backplane is comprising of a network of optical waveguides which can guide polarized light. Furthermore, the backplane has magneto optic routers for steering light at the vertexes of the network, and the backplane also has optical devices for operationally connecting the processing units to the network. The backplane network affords an optical interconnection amongst all of the processing units.

Abstract: A display device and method for fabricating a liquid crystal cell are disclosed. A liquid crystal cell includes a first substrate, and a second substrate attached to the first substrate. The first substrate has a same thickness as the second substrate. The first substrate is lapped at a first rate while concurrently lapping the second substrate at a second rate, which is different from the first rate. The first substrate and the second substrate are thinned to different thicknesses. The thinner of the first and second substrates is provided on a viewer side of a collimate and post diffuse type liquid crystal cell to reduce depixelization.

Abstract: The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including an ultra-thin top Si-containing layer and at least one patterned buried semi-insulating or insulating region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form a first implant region of the first ions in the Si-containing substrate. Following the implantation of first ions, a first annealing step is performed which forms a buried semi-insulating or insulating region within the Si-containing substrate. Next, second ions that are insoluble in the semi-insulating or insulating region are selectively implanted into portions of the buried semi-insulating or insulating region. After the selective implant step, a second annealing step is performed which recrystallizes the buried semi-insulating or insulating region that includes second ions to the same crystal structure as the original Si-containing substrate.

Abstract: Slurry compositions comprising an oxidizing agent, optionally a copper corrosion inhibitor, abrasive particles; surface active agent, a service of chloride and a source of sulfate ions.