Abstract: A method of fabricating a defect induced buried oxide (DIBOX) region in a semiconductor substrate utilizing an oxygen ion implantation step to create a stable defect region; a low energy implantation step to create an amorphous layer adjacent to the stable defect region, wherein the low energy implantation steps uses at least one ion other than oxygen; oxidation and, optionally, annealing, is provided. Silicon-on-insulator (SOI) materials comprising a semiconductor substrate having a DIBOX region in patterned or unpatterned forms is also provided herein.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract: An organic polymer film can be completely decomposed and removed from a substrate surface by exposing the film to ultraviolet radiation having a wavelength of 180 nm or less. Also, ultraviolet radiation not longer than 180 nm in wavelength is scarcely transmitted through a transparent conductive oxide such as ITO and, thus, can be used for eliminating a defective polyimide alignment film formed on a color filter substrate and an array substrate having a transparent electrode pattern of ITO formed on the surface of a pigment portion and a TFT structure, respectively. According to the present invention, the defective alignment film on the substrates can be removed completely without any damage such as discoloring of the pigment portion and/or changing the TFT characteristics.

Abstract: The liquid crystal display is a “Cs on Gate type” active matrix liquid crystal display in which an auxiliary capacitor is formed by each pixel electrode and an adjacent gate line. By driving gate lines sequentially line by line to control the potential of the pixel electrode through the auxiliary capacitor Cs at a predetermined time before one frame period ends, a blanking (BL) writing is performed, thereby for forcedly blanking a display.

Abstract: A method of forming a silicate dielectric having superior electrical properties comprising forming a metal oxide layer on a Si-containing semiconductor material and reacting the metal oxide with the underlying Si-containing material in the presence of an oxidizing gas is provided. Semiconductor structures comprising the metal silicate formed over a SiO2 layer are also disclosed herein.

Abstract: The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.

Abstract: A method of reducing the contact resistance of metal silicides to the p+ silicon area or the n+ silicon area of the substrate comprising: (a) forming a metal germanium (Ge) layer over a silicon-containing substrate, wherein said metal is selected from the group consisting of Co, Ti, Ni and mixtures thereof; (b) optionally forming an oxygen barrier layer over said metal germanium layer; (c) annealing said metal germanium layer at a temperature which is effective in converting at least a portion thereof into a substantially non-etchable metal silicide layer, while forming a Si—Ge interlayer between said silicon-containing substrate and said substantially non-etchable metal silicide layer; and (d) removing said optional oxygen barrier layer and any remaining alloy layer. When a Co or Ti alloy is employed, e.g.

Abstract: A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon <1020 cm−3, the as-grown p- or n-type dopant profile can withstand furnace anneals to temperatures of 850° C. and rapid thermal anneal temperatures to 1000° C.

Abstract: An ultra high-speed DDP-SRAM (Dual Dual-Port Static Random Access Memory) cache having a cache speed in approximately the GHz range. This is accomplished by (1) a specially designed dual-port SRAM whose size is slightly larger than that of a conventional single port SRAM, and (2) the use of a dual dual-port SRAM architecture which doubles its speed by interleaved read and write operations. A first embodiment provides a 6-T (transistor) all nMOS dual-port SRAM cell. A second embodiment provides a dual port 7T-SRAM cell which has only one port for write, and both ports for read.

Abstract: To increase support a screen having a different aspect ratio or a large screen by use of existing graphics adapters, thus improving performance and flexibility of the whole system. Disclosed is a monitor system comprising a liquid crystal display having a liquid crystal panel which displays an image and has a display area virtually divided into a plurality of divided area, and a plurality of graphics adapters to for developing image data for the divided areas of the liquid crystal display, wherein the divided areas of a screen in the liquid crystal display are obtained by further dividing an area in which the graphics adapters to create images, and a reconstruction circuit for reading out image data developed in the graphics adapters in turn to reconstruct the image data is provided.

Abstract: A head mounted virtual image display unit is provided which is compact in size and weight, and incorporates a high performance optical system offering a clear see-through capability. A sliding light shield may be incorporated for those instances when see-through capability is not desired. A focus adjustment may be incorporated to permit the focusing of the image, for example, at a distance of approximately 18 inches to infinity. An adjustable headband may be incorporated that adapts to fit the users head. A flexible boom structure may be incorporated to facilitate fine positional adjustment of the optical assembly. A slider and ball joint mechanism may also be incorporated to facilitate positional adjustment of the optical assembly. A built-in microphone may be incorporated to enable speech input by the user.

Abstract: A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate is provided by implanting oxygen into a Si/SiGe multilayer heterostructure which comprises alternating Si and SiGe layers. Specifically, the high quality, relaxed SiGe-on-insulator is formed by implanting oxygen ions into a multilayer heterostructure which includes alternating layers of Si and SiGe. Following, the implanting step, the multilayer heterostructure containing implanted oxygen ions is annealed, i.e., heated, so as to form a buried oxide region predominately within one of the Si layers of the multilayer structure.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics.

Abstract: An apparatus and method is described incorporating one or more layers of SiCOH and one or more layers of patterned conductors in an integrated circuit chip. The invention overcomes the problem of capacitance by lowering the k of the delectric and overcomes the problem of breakdown voltage and the leakage curent by tailoring the composition of SiCOH.

Abstract: There is provided a method for driving an organic light emitting diode (OLED) pixel circuit. The method includes applying a first signal to a terminal of the OLED when setting a state of the pixel circuit, and applying a second signal to the terminal when viewing the state. There is also provided a driver for an OLED pixel circuit, where the driver employs this method.

Abstract: In the liquid crystal display 10, consisting of a first substrate (12) and a second substrate (14) facing each other, either or both of the first substrate (12) and the second substrate (14) is/are disposed in a non-display region, the spacers 18 consisting of a photosensitive resin regulating the cell gaps 16 between both substrates 12 and 14, and liquid crystal 20 sandwiched between the first substrate (12) and the second substrate (14), either a dynamic hardness value or a plastic deformation hardness value is within a fixed range.

Abstract: Display panels and methods for fabrication are disclosed for an in-plane switching mode display to reduce or eliminate image sticking. The display panel includes a substrate with a first electrode formed on the substrate. A dielectric layer is formed on the substrate, and the dielectric layer forms an opening down to the first electrode so that the dielectric layer is eliminated over the first electrode. A second electrode is formed on the dielectric layer, and an alignment layer is formed on the first electrode, the second electrode and the dielectric layer.

Abstract: An active matrix organic light-emitting diode comprising an organic light-emitting diode portion. The organic light-emitting diode portion comprising: an underlayer having a top surface and bottom surface; a first electrode layer which is deposited and patterned on the top surface of the underlayer such that at least a portion of the underlayer is exposed, wherein the deposited first electrode layer comprises a top surface, a bottom surface and sidewalls disposed between the top and bottom surfaces, the sidewalls are positioned adjacent to the exposed portion of the underlayer; a passivation layer deposited on the exposed portion of the underlayer and the peripheral regions of the first electrode layer such that the passivation layer covers the sidewalls and the peripheral regions of the first electrode layer; a transparent conductor layer deposited on the passivation layer and the non-peripheral regions of the first electrode layer; and a second electrode layer deposited on the transparent conductor layer.

Abstract: The present invention discloses a multi-diameter electrical conductor for use as an embedded plug in a microelectronic device. The multi-diameter electrical conductor consists of a body portion which has a first diameter, and at least one neck portion in contact with the body portion that has at least a second diameter smaller than the first diameter. In a preferred embodiment, the multi-diameter conductor is a dual-diameter conductor providing electrical communication between an electrode and an active circuit element in a semiconductor structure and comprising a lower body portion and an upper neck portion. The conductive materials used in forming the body portion and the neck portion of the contact plug can be selected from doped polysilicon, refractory metals, metal silicides, low resistivity metals, noble metals and their alloys, adhesion layers, metallic diffusion barrier layers, and oxide and nitride diffusion barrier materials.