Abstract: A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

Abstract: A liquid crystal display device includes a first substrate, a dry alignment film deposited over the substrate, a second substrate coupled to the first substrate with the dry alignment film deposited over the second substrate therebetween and forming a cell gap, and a liquid crystal material formed in the cell gap. The dry alignment film allows for a truly vertical alignment of molecules of the liquid crystal material such that the molecules form an angle of substantially 90° relative to the substrate. The dry alignment film can be an oxide layer, a nitride layer, an oxynitride layer or a silicon layer. This dry alignment layer can be treated to form a tilted homeotropic alignment, such that the liquid crystal molecules have a pretilt angle of 0.5 to 10 degrees from a substrate normal direction.

Abstract: A structure and method of forming an abrupt doping profile is described incorporating a substrate, a first epitaxial layer of Ge less than the critical thickness having a P or As concentration greater than 5×1019 atoms/cc, and a second epitaxial layer having a change in concentration in its first 40 Å from the first layer of greater than 1×1019 P atoms/cc. Alternatively, a layer of SiGe having a Ge content greater than 0.5 may be selectively amorphized and recrystalized with respect to other layers in a layered structure. The invention overcomes the problem of forming abrupt phosphorus profiles in Si and SiGe layers or films in semiconductor structures such as CMOS, MODFET's, and HBT's.

Abstract: There is provided a method for fabricating an organic light emitting device. The method includes depositing a first electrode layer on a substrate, depositing an electrically insulating layer on the first electrode layer, depositing a second electrode layer on the insulating layer, depositing an organic layer on the second electrode layer, forming an aperture in the organic layer, depositing a light transmissive electrically conductive layer on the organic layer, and forming an electrical connection between the conductive layer and one of the first and second electrode layers via the aperture.

Abstract: A means for fabrication of solenoidal inductors integrated in a semiconductor chip is provided. The solenoidal coil is partially embedded in a deep well etched into the chip substrate. The non-embedded part of the coil is fabricated as part of the BEOL metallization layers. This allows for a large cross-sectional area of the solenoid turns, thus reducing the turn-to-turn capacitive coupling. Because the solenoidal coils of this invention have a large diameter cross-section, the coil can be made with a large inductance value and yet occupy a small area of the chip. The fabrication process includes etching of a deep cavity in the substrate after all the FEOL steps are completed; lining said cavity with a dielectric followed by fabrication of the part of the coil that will be embedded by deposition of a conductive material metal through a mask; deposition of dielectric and planarization of same by CMP.

Abstract: A method of forming a silicon-on-insulator (SOI) substrate having a buried oxide region that has a greater content of thermally grown oxide as compared to oxide formed by implanted oxygen ions is provided. Specifically, the inventive SOI substrate is formed by utilizing a method wherein oxygen ions are implanted into a surface of a Si-containing substrate that includes a sufficient Si thickness to allow for subsequent formation of a buried oxide region in the Si-containing substrate which has a greater content of thermally grown oxide as compared to oxide formed by the implanted oxygen ions followed by an annealing step.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: A polishing pad having a body comprising fibers embedded in a matrix polymer formed by a reaction of polymer precursors. The fibers define interstices, and the precursors fill these interstices substantially completely before completion of the reaction. The pad may include a thin layer of free fibers at its polishing surface. A segment of at least a portion of the free fibers are embedded in the adjacent body of the polymer and fibers. The fibers may be separate, or in the form of a woven or non-woven web.

Abstract: A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of Cu electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.

Abstract: An apparatus and a method for filling high aspect ratio holes in electronic substrates that can be advantageously used for filling holes having aspect ratios larger than 5:1 are disclosed. In the apparatus, a filler plate and a vacuum plate are used in conjunction with a connection means such that a gap is formed between the two plates to accommodate an electronic substrate equipped with high aspect ratio via holes. The filler plate is equipped with an injection slot while the vacuum plate is equipped with a vacuum slot such that when a substrate is sandwiched therein, via holes can be evacuated of air and injected with a liquid simultaneously from a bottom side and a top side of the substrate. The present invention novel apparatus and method allows the filling of via holes that have small diameters, i.e., as small as 10 &mgr;m, and high aspect ratios, i.e.

Abstract: A method to obtain thin (<300 nm) strain-relaxed Si1−xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. <106 cm−2. The approach begins with the growth of a pseudomorphic Si1−xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1−xGex interface, parallel to the Si(001) surface.

Abstract: A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.

Abstract: A circumferential area of a liquid-crystal cell is provided with a common wiring, a gate wiring, a source wiring, and an alignment film. The alignment film is insulated from the gate wiring and the source wiring by an insulating film. The common wiring is provided with a common-potential exposure portion through an opening formed on the insulating film and electrically connected with the alignment film. Because a common potential close to an average potential of cells is supplied to the alignment film, it is possible to prevent screen display troubles and deterioration caused by impurity ions remaining on the surface or the inside of the alignment film.

Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

Abstract: A non-ablative structure and method for forming a variable resistor includes providing a programmable resistive element including two or more different conductive materials, and changing a resistance of the programmable resistive element to a finite value by heating the programmable element by either providing a current flow through the programmable element, or directing a laser beam onto the programmable element. The conductive materials are interdiffused to form an alloy of the conductive materials. A resistance value of the variable resistor is determined, at least in part, by the degree to which the conductive materials are alloyed or interdiffused. The method and structure of the variable resistor prevents ablative damage to adjoining circuit structure, allowing tighter pitch, and has application to digital programmable elements, and to resistance trimming for impedance matching in RF integrated circuits.

Abstract: A method and apparatus for refreshing data in a dynamic random access memory (DRAM) cache memory in a computer system are provided to perform a data refresh operation without refresh penalty (e.g., delay in a processor). A data refresh operation is performed with respect to a DRAM cache memory by detecting a request address from a processor, stopping a normal refresh operation when the request address is detected, comparing the request address with TAG addresses stored in a TAG memory, generating refresh addresses to refresh data stored in the cache memory, each of which is generated based on an age of data corresponding to the refresh address, and performing a read/write operation on a wordline accessed by the request addresses and refreshing data on wordlines accessed by the refresh addresses, wherein the read/write operation and the refreshing of data are performed simultaneously.

Abstract: The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.

Abstract: Grooves are formed in a CMP pad by positioning the pad on a supporting surface with a working surface of the pad in spaced relation opposite to a router bit and at least one projecting stop member adjacent to the router bit, an outer end portion of the bit projecting beyond the stop. When the bit is rotated, relative axial movement between the bit and the pad causes the outer end portion of the bit to cut an initial recess in the pad. Relative lateral movement between the rotating bit and the pad then forms a groove which extends laterally away from the recess and has a depth substantially the same as that of the recess. The depths of the initial recess and the groove are limited by applying a vacuum to the working surface of the pad to keep it in contact with the stop member(s). Different lateral movements between the bit and the pad are used to form a variety of groove patterns, the depths of which are precisely controlled by the stop member(s).

Abstract: The present invention provides a method and apparatus for color adjustment of a display screen which can provide an interactive user interface which allows a user to perform color adjustment efficiently and effectively. The color adjustment of the display screen in a color display device, such as LCD, CRT or the like, is performed by displaying a color image without any color adjustment at a certain portion of the display screen, displaying a color image with a color adjustment at another portion of the display screen, and referring to the color image without any color adjustment. And to implement this method for color adjustment, the apparatus is configured so that the color images which have passed the color adjustment block and have their colors adjusted, and the color images which have not passed the color adjustment block and are not subject to the color adjustment can be both displayed on the same display screen.