Abstract: The present invention embodies high-accuracy white point adjustment with a simple circuit configuration according to an efficient algorithm in a display system for full digital processing. More particularly, the present invention is directed to a digital video interface 13 for inputting a digital video signal outputted from a host system and a liquid-crystal display monitor 11 for applying color conversion to the digital video signal inputted by the digital video interface 13 without using a look-up table, in which an adjusted-value input logic for inputting adjusted values at predetermined points to achromatic colors between maximum- and minimum-gray-scale achromatic colors and a controller LSI 22 for computing a digital video signal inputted by the digital video interface 13 so as to converge chromaticity coordinates for achromatic colors and outputting a computed digital value in a pipeline manner are used.

Abstract: A method is described for repairing failure points, regions or locations in an electronic device to have a perfect function when a semiconductor device including an LCD or other electronic device has defects. Described is a method of transferring a single or multi-layer thin film piece into a recess with the physical properties of the thin film piece unchanged. An electronic device is described incorporating a substrate; and a plurality of thin films laminated on the substrate and part of the thin films are formed on a predetermined circuit pattern, wherein a transfer film for repairing a defect is fitted into a recess where the low layers of the thin films are exposed by removing part of a single or multi-layer thin films covering a defective portion included on the thin films and its surrounding portion.

Abstract: A method of producing electrical contacts having reduced interface roughness as well as the electrical contacts themselves are disclosed herein. The method of the present invention comprises (a) forming an alloy layer having the formula MX, wherein M is a metal selected from the group consisting of Co and Ni and X is an alloying additives over a silicon-containing substrate; (b) optionally forming an optional oxygen barrier layer over said alloy layer; (c) annealing said alloy layer at a temperature sufficient to form a MXSi layer in said structure; (d) removing said optional oxygen barrier layer and any remaining alloy layer; and optionally (e) annealing said MXSi layer at a temperature sufficient to form a MXSi2 layer in said structure.

Abstract: The object of the present invention is to reduce the number of inputs to LCD driver chips, and to suppress the occurrence of variances between the chips. A ten bit wide binary counter 202 is self activated in synchronization with a system clock. Each of multiple five-step shift registers 200 having ten bit widths stores gamma compensation data received from a PC. Each of multiple comparators 204 compares a binary counter value (X) with a value (Y) stored in a ten bit wide five-step shift register 200, and converts the gamma compensation data into a pulse width. The output of each comparator 204 is latched by each of multiple D-FFs 206 in synchronization with the system clock, and each of multiple time/voltage converters 208 passes the output of a D-FF 206 through an LPF and generates a reference gamma compensation voltage.

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to the diffusion of Ge. Optionally forming a Si cap layer over the SiGe or pure Ge layer, and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughout the first single crystal Si layer, the optional Si cap and the SiGe or pure Ge layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate materials are also disclosed herein.

Abstract: Described herein is a method for delineating crystalline defects in a thin Si layer over a SiGe alloy layer. The method uses a defect etchant with a high-defect selectivity in Si. The Si is etched downed to a thickness that allows the defect pits to reach the underlying SiGe layer. A second etchant, which can be the same or different from the defect etchant, is then used which attacks the SiGe layer under the pits while leaving Si intact.

Abstract: Viewing angle characteristics of a liquid crystal display (LCD) are improved by reducing the number of subpixels in an image with mid-tone luminance values. In a preferred embodiment, a first table of entries associating subpixel intensity values and subpixel luminance values for a LCD in at least one viewing angle direction is provided. A target intensity value is determined from the first table, corresponding to the average subpixel luminance over a small number of adjacent subpixels. A second table of entries associates the target intensity values with intensity values above and below the target. The adjacent subpixel intensity values are modified according to the second table, thereby reducing the number of subpixels with mid-tone luminance values. The subpixel data is preferably processed within a portion of an application-specific integrated circuit (ASIC), contained within the display module.

Abstract: The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leakage current from another signal line. A thin film transistor comprises a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer 27 formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk leakage current flowing from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.

Abstract: A patterned SOI/SON composite structure and methods of forming the same are provided. In the SOI/SON composite structure, the patterned SOI/SON structures are sandwiched between a Si over-layer and a semiconductor substrate. The method of forming the patterned SOI/SON composite structure includes shared processing steps wherein the SOI and SON structure are formed together. The present invention also provides a method of forming a composite structure which includes buried conductive/SON structures as well as a method of forming a composite structure including only buried void planes.

Abstract: A liquid crystal device (and method for forming the LCD) includes a first transparent substrate having a first surface and a second surface, and a second transparent substrate having a first surface and a second surface. The first transparent substrate and the second transparent substrate are arranged such that the first surface of the first transparent substrate faces the first surface of the second transparent substrate, and a liquid crystal material is enclosed between the first surface of the first transparent substrate and the first surface of the second transparent substrate. A pixel array, in which a plurality of pixel regions are arranged in row and column directions and data signals are applied to the pixel regions through data lines, is formed on the first surface of the first transparent substrate and the first surface of the second transparent substrate.

Abstract: A liquid crystal (LC) lightvalve comprising a twisted nematic LC layer whose molecules are aligned with pixel edges at the mirror backplane, thereby providing improved contrast and efficiency, and reduced visibility of post spacers in black state. The present invention is directed to an LC structure wherein the backplane is rubbed in a direction rectilinear with pixel edges. The LC layer is given the same twist rotation and birefringence as in the conventional TN lightvalve. Polarization control is maintained by illuminating the lightvalve with light whose polarization is rotated by the twist angle relative to the x,y, pixel axes, and by collecting the orthogonally polarized component of the reflected light. The lightvalve top glass is thus rubbed in a direction which is rotated by the twist angle from the horizontal or vertical direction at which the backplane is rubbed.

Abstract: A liquid crystal display panel (and a method for manufacturing the liquid crystal display panel) includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion.

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

Abstract: A method for fabricating a thermally stable ultralow dielectric constant film comprising Si, C, O and H atoms in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition (“PECVD”) process is disclosed. Electronic devices containing insulating layers of thermally stable ultralow dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable ultralow dielectric constant film, specific precursor materials are used, such as, cyclic siloxanes and organic molecules containing ring structures, for instance, tetramethylcycloterasiloxane and cyclopentene oxide.

Abstract: In a liquid crystal display device of a direct view type, a lenticular lens sheet is provided in the backside of a liquid crystal display panel. Light emitted to a lens of the lenticular lens sheet is first converged in the liquid crystal display panel, and then diffused. When the light is emitted from the liquid crystal display panel, the radiation distribution thereof is widened. Thus, a bright display screen even when seen from a wide angle can be realized.

Abstract: The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si-film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.

Abstract: Disclosed are an inspection method for a disconnection of a storage capacitor line and an inspection device for the same in an inspection of an array substrate used in a liquid crystal display apparatus. An inspection method for an array substrate is constituted, in which a quantity of charges stored in the storage capacitor becomes C (Vd1−Vcs1) by supplying simultaneously a pulse signal Vd and a pulse signal Vcs to the storage capacitor from a signal line and a Cs line on a TFT array substrate, and an influence of the disconnection of the Cs line is taken into consideration when the above-described quantity of charges is detected in a reading circuit. Note that the above-described inspection is performed not for all the storage capacitors, but for one storage capacitor in each Cs line. Thus, the inspection for all the Cs lines in liquid crystal panels from 14 inch diagonal to 18 inch diagonal is terminated in about 1 to 2 seconds.

Abstract: A barrier material that is particularly suited as a barrier layer in copper interconnects structures found in semiconductor structures. The barrier layer contains one or more regions with one region containing at least 50 atom percent of a copper interface metal. The copper interface metal is selected from ruthenium, rhodium, palladium, silver, gold, platinum, iridium, selenium, tellurium, or alloys thereof. The barrier layer also contains a dielectric interface material.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: A method to selectively cap a cooper BEOL terminal pad with a Cu/Sn/Au alloy. The method includes providing one or more Cu BEOL terminal pads and coating the pads with a Sn coating followed by coating the Sn with a Au coating. The coated pads are then annealed to form the Cu/Sn/Au capping alloy.