Abstract: A reflective liquid crystal lightvalve for modulating the polarization of incident light within a specified band of wavelengths into on and off states, comprises: (i) a pixelated reflective backplane; (ii) a first liquid crystal layer, positioned proximate the pixelated reflective backplane, the first liquid crystal layer being tuned in the off state to switch incident light at the center of the specified band of wavelengths into a state that is not fully off; and (iii) a second liquid crystal layer, positioned proximate the first liquid crystal layer wherein the first liquid crystal layer is positioned between the second liquid crystal layer and the pixelated reflective backplane, the second liquid crystal layer having a birefringence which, at a given depth within its thickness, is substantially equal and opposite to a birefringence of a layer within the first liquid crystal layer that is located at a matching distance from a midplane separating the first and second liquid crystal layers.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.

Abstract: Slurry compositions comprising abrasive particles and solid lubricant particles are useful for planarizing surfaces, and preventing delamination and scratches.

Abstract: An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

Abstract: A projection display system includes a light source, wavelength-selective retarder device, first and second reflective light valves (LVs), a polarizing beam splitter (PBS), and a wavelength-selective filtering device. The wavelength-selective retarder device receives a uniformly polarized light from the light source and produces a first dark-state light having a first polarization state at a first set of wavelengths and a second dark-state light having a second polarization state at a second set of wavelengths. The first LV receives the first dark-state light and produces a first bright-state light by rotating the polarization from the first polarization state to the second polarization state. The second LV receives the second dark-state light and produces a second bright-state light by rotating the polarization from the second polarization state to the first polarization state.

Abstract: The present invention includes a method of forming an aligned film on a substrate. The film is deposited and aligned in a single step by a method comprising the step of bombarding a substrate with an ion beam at a designated incident angle to simultaneously (a) deposit the film onto the substrate and (b) arrange an atomic structure of the film in at least one predetermined aligned direction.

Abstract: An organic light emitting device (and a method for producing the device) includes a multilayered structure with a substrate layer providing a first electrode layer, a second electrode layer and at least one layer of light emitting organic material between the first and second electrode layers. The second electrode layer includes at least two separate layers, a layer of a semi-transparent metal electrode and a layer of light transparent lateral conductor, is deposited onto the layer of light emitting organic material such as depositing the semi-transparent metal electrode layer onto the layer of light emitting organic material, depositing subsequently at least one protection layer thereupon and depositing the light transparent lateral conductor layer onto the protection layer.

Abstract: A method for patterning an indium-tin-oxide (ITO) film by using a chemically amplified resist, causing no resist separation nor adhesion degradation even if the ITO film is exposed to white light after the resist development. An amorphous ITO film is formed on a wafer. A negative chemically amplified resist is applied directly to the ITO film, and the resist film is exposed and developed. The structure having a resist pattern on the amorphous ITO film is free from resist separation and adhesion degradation even if the resist pattern is exposed to white light, and therefore the later manufacturing steps are not adversely affected, enabling proper visual inspection. After the structure is judged to be acceptable at the visual inspection, the amorphous ITO film is etched using the resist pattern as a mask, and then the resist pattern is removed.

Abstract: A centralized power supply system for a multi-system on chip device includes: an external power supply for supplying power to the device; a centralized DC generator macro having generator components for receiving the external power supplied and generating therefrom one or more power supply voltages for use by surrounding system macros provided on the multi-system chip, the centralized DC generator macro further distributing the generated power supply voltages to respective system macros. A noise blocking structure is provided that surrounds the centralized DC generator system and isolates the centralized DC generator system from the surrounding system macros.

Abstract: A compact SRAM cell that incorporates refractory metal-silicon-nitrogen resistive elements as its pull-up transistors is described which includes a semi-conducting substrate, a pair of NMOS transfer devices formed vertically on the sidewalls of an etched substrate by a metal conductor providing electrical communication between an n+ region in the substrate and a bitline on top, a pair of pull-down nMOS devices on the substrate connected to ground interconnects, and a pair of vertical high-resistive elements formed of a refractory metal-silicon-nitrogen and function as a load for connecting to Vdd. The invention further describes a method for fabricating such compact SRAM cell.

Abstract: A liquid crystal display structure, includes a glass substrate and at least one or more chips mounted on the glass substrate including flexible printed circuit connect pins. A common wiring for connecting the at least one or more chips to a flexible printed circuit is formed on the glass substrate. The common wiring is connected to the flexible printed circuit connect pins of the at least one or more chips and to the flexible printed circuit at at least one position on the common wiring.

Abstract: A liquid crystal display device and an electro-optical device include substrates facing each other and each having an electrode, the substrates being spaced apart, spacers disposed between the substrates and defining an electro-optical cell together with the substrates, and a colloidal liquid crystal composite (CLCC) formed in the electro-optical cell. The CLCC includes particle-rich inter-domain regions and micro-domains of a mesogenic liquid crystal, and the particle-rich inter-domain regions include colloidal organic particles being networked in the mesogenic liquid crystal.

Abstract: A method and apparatus for controlling tint in a digital color display system capable of efficiently performing tint control of displayed colors. The tint control method is executed according to the following: (1) when the maximum and the minimum among R, G, B are the maximum gray scale value and the minimum gray scale value respectively, a step of transforming the input color into a color of a different tint based on a use defined maximum transformation value and a transformation direction; (2) when the maximum and the minimum among R, G, B are Dmax and Dmin respectively, a step of transforming the input color into a color of a different tint based on a smaller transformation value and the same transformation direction; and (3) when all values R, G, B are equal, a step of not transforming the input color in accordance with any input set value.

Abstract: An active matrix reflective liquid crystal device includes an array substrate which includes switching elements corresponding to pixels and an array of pixel electrodes connected to the switching elements; and an opposing substrate which has a transparent electrode opposite the array of pixel electrodes with a liquid crystal layer inserted therebetween. Each of the pixel electrodes includes an array of electrode studs, (e.g., divided electrode elements). The regions between the electrodes are filled with an insulating material, and the surface of the stud array is planarized by chemical-mechanical polishing (CMP). A dielectric light reflective film is formed on the planarized surface of the stud array, and a liquid crystal molecule alignment film is deposited thereon.

Abstract: The present invention provides a method of fabricating a TFT structure by two masking processes. More specifically, a light shielding layer and an interlayer insulating layer are sequentially formed on a substrate, and then source/drain electrodes are formed on the interlayer insulating layer (a first masking step). A semiconductor layer, a gate insulating layer and a gate metal layer are sequentially formed so as to cover the source/drain electrodes, and a gate electrode is formed in a second masking step. Subsequently, the gate insulating layer and the semiconductor layer are etched, and the interlayer insulating layer and the light shielding layer, which are disposed under the source/drain electrodes, are etched using the source/drain electrodes as a mask, thus obtaining a top gate TFT structure.

Abstract: A silicon-on-insulator substrate having improved thickness uniformity as well as a method of fabricating the same is provided. Specifically, improved thickness uniformity of a SOI substrate is obtained in the present invention by subjecting a bonded or SIMOX (separation by ion implantation of oxygen) SOI substrate to a high-temperature oxidation process that is capable of improving the thickness uniformity of said SOI substrate. During this high-temperature oxidation process surface oxidation of the superficial Si-containing (i.e., the Si-containing layer present atop the buried oxide (BOX) region) occurs; and (ii) internal thermal oxidation (ITOX), i.e., diffusion of oxygen via the superficial Si-containing layer into the interface that exists between the BOX and the superficial Si-containing layer also occurs.

Abstract: A display device provides a first optical device disposed in a light path for spatially separating angularly separated light into color components, and a pixel which receives each of the color components through a sub-pixel. Each sub-pixel controls transmitted light intensity therethrough. A black matrix is formed in operative relationship with the sub-pixels including apertures for receiving the color components. A microstructured layer is disposed in the light path and receives or transmits the color components from or to the apertures of the black matrix. The microstructured layer includes tilted and/or curved surfaces for redirecting laterally shifted color components shifted by the first optical device and may also diffuse light.

Abstract: A multi-port memory array is associated with wordlines and bit-lines to perform data read/write operation and has multi-port memory cells each of which includes multiple ports through which the wordlines and bit-lines are provided, multiple transistor devices each of which corresponds to each of the multiple ports and is coupled to a wordline and a bit-line through a corresponding port, each transistor device being gated by a wordline and having a conduction path of which a first end is connected to a bit-line, and a charge storage device commonly connected to a second end of a conduction path of each of the transistor devices, where the charge storage device is charged when any of the plurality of transistor devices is activated.

Abstract: A method for tailoring properties of high k thin layer perovskite materials, and devices comprising such insulators are herein presented. The method comprise the steps of, first, substantially completing the manufacture of a device, which device contains the high k insulator in a polycrystalline form. The device, such as a capacitor, or an FET, went through the typically high temperature manufacturing process of a fabrication line. In the next step, the device is in situ ion implanted with such a dose and energy to convert a fraction of the polycrystalline material into an amorphous material state, hereby tailoring the properties of the insulator. The fraction of polycrystalline material converted to amorphous material might be 1. This process can be applied to many electronic devices and some optical devices. The process results in novel perovskite thin layer materials and novel devices fabricated with such materials.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of the first ions in the Si-containing substrate. Following the first implant step, a selective implant process is employed wherein second ions that are insoluble in SiO2 are incorporated into portions of the Si-containing substrate. The second ions employed in the selective implant step are capable of preventing the implant region of first ions from forming an oxide region during a subsequent annealing step. An annealing step is then performed which causes formation of a buried oxide region in the implant region of first ions that does not include the second ions.