Abstract: A method to obtain thin (<300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. <106 cm−2. The approach begins with the growth of a pseudomorphic Si1-x Gex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operating with this method is dislocation nucleation at He-induced platelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

Abstract: Organic addition agents in copper plating baths are monitored by diluting a sample of the bath with sulfuric acid and hydrochloric acid and optionally a cupric salt. The diluting provides a bath having conventional concentrations of cupric ion, sulfuric acid and hydrochloric acid; and adjusted concentrations of the organic addition agents of 1/X of their original values in the sample; where X is the dilution factor. CVS techniques are used to determine concentrations of organic addition agents.

Abstract: A method for forming a copper conductor in an electronic structure by first depositing a copper composition in a receptacle formed in the electronic structure, and then adding impurities into the copper composition such that its electromigration resistance is improved. In the method, the copper composition can be deposited by a variety of techniques such as electroplating, physical vapor deposition and chemical vapor deposition. The impurities which can be implanted include those of C, O, Cl, S and N at a suitable concentration range between about 0.01 ppm by weight and about 1000 ppm by weight. The impurities can be added by different methods such as ion implantation, annealing and diffusion.

Abstract: A liquid crystal display which comprises a light guide 2 placed at the back of a liquid crystal display panel 1; a first fluorescent tube 3 disposed along at least one side of the light guide 2; a second fluorescent tube 4 disposed adjacent to the first fluorescent tube 3; and a shielding component 5 for shielding an incoming light directly entering from the second fluorescent tube 4 into the first fluorescent tube 3, to reduce a deterioration of luminance that can occur in a backlight for a liquid crystal display panel.

Abstract: A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complementary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.

Abstract: A transistor, in accordance with the present inventions includes a gate electrode layer formed on a substrate and an insulating layer formed on the gate electrode layer. A first conductive layer forms a first portion and a second portion separated by a gap therebetween. The gap is formed at a position corresponding to a gate electrode in the gate electrode layer. A doping layer is formed on the first portion and the second portion of the first conductive layer, forming a source and a drain for the transistor. A semiconductor layer is formed over the doping layer of the first portion and the second portion and in the gap in contact with the insulating layer such that upon activation of the gate electrode current flows across the gap directly between the first portion and the second portion in the first conductive layer. Methods for fabrication and other embodiments are also included.

Abstract: A chip packaging system and method for providing enhanced thermal cooling including a first embodiment wherein a diamond thin film is used to replace at least the surface layer of the existing packaging material in order to form a highly heat conductive path to an associated heat sink. An alternative embodiment provides diamond thin film layers disposed on adjacent surfaces of the chip and the chip package. Yet another alternative embodiment includes diamond thin film layers on adjacent chip surfaces in a chip-to-chip packaging structure. A final illustrated embodiment provides for the use of an increased number of solder balls disposed in at least one diamond thin film layer on at least one of a chip and a chip package joined with standard C4 technology.

Abstract: A method of making a light-emitting device comprises forming a first and second components. The first component has a first substrate, a first electrode on the first substrate, an organic layer on the first electrode, and a light-transmissive second electrode on the organic layer. The second component has a light-transmissive second substrate, and a light transmissive, electrically conductive layer on the second substrate. The first and second components are joined with the second electrode of the first component facing the conductive layer of the second component. An electrical contact is formed between the second electrode of the first component and the electrically conductive layer of the second component.

Abstract: The present invention provides a method of fabricating a thermally stable polysilicon/high-k dielectric film stack utilizing a deposition method wherein Si-containing precursor gas which includes silicon and hydrogen is diluted with an inert gas such as He so as to significantly reduce the hydrogen content in the resultant polysilicon film. Semiconductor structures such as field effect transistors (FETs) and capacitors which include at least the thermally stable polysilicon/high-k dielectric film stack are also provided herein.

Abstract: Thermal cooling structures of diamond or diamond-like materials are provided for conducting heat away from semiconductor devices. A first silicon-on-insulator embodiment comprises a plurality of thermal paths, formed after shallow trench and device fabrication steps are completed, which extend through the buried oxide and provide heat dissipation through to the underlying bulk silicon substrate. The thermal conduction path material is preferably diamond which has high thermal conductivity with low electrical conductivity. A second diamond trench cooling structure, formed after device fabrication has been completed, comprises diamond shallow trenches disposed between the devices and extending through the buried oxide layer. An alternative diamond thermal cooling structure includes a diamond insulation layer deposited over the semiconductor devices in either an SOI or bulk silicon structure.

Abstract: A method for forming metal interconnect in a semiconductor structure and the structure formed are disclosed. In the method, a seed layer of a first metal is first deposited into an interconnect opening wherein the seed layer has an average grain size of at least 0.0005 &mgr;m. The semiconductor structure is then annealed at a temperature sufficient to grow the average grain size in the seed layer to at least the film thickness. A filler layer of a second metal is then deposited to fill the interconnect opening overlaying the seed layer such that the filler layer has an average grain size of larger than 0.0005 &mgr;m and comparable to the annealed seed layer.

Abstract: The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.

Abstract: A method for direct chip attach of a semiconductor chip to a circuit board by using solder bumps and an underfill layer is disclosed. In the method, a layer of in-situ polymeric mold material is first screen printed on the top surface of the semiconductor chip exposing a multiplicity of bond pads. The in-situ polymeric mold layer is formed with a multiplicity of apertures which are then filled with solder material in a molten solder screening process to form solder bumps. A thin flux-containing underfill material layer is then placed on top of a circuit board over a plurality of conductive pads which are arranged in a mirror image to the bond pads on the semiconductor chip. The semiconductor chip and the circuit board are then pressed together with the underfill layer inbetween and heated to a reflow temperature of higher than the melting temperature of the solder material until electrical communication is established between the bond pads and the conductive pads.

Abstract: An insulator for covering an interconnection wiring level in a surface thereof on a semiconductor substrate containing semiconductor devices formed by curing a flowable oxide layer and annealing. The annealing is carried out in the presence of hydrogen and aluminum to obtain a dielectric constant of the oxide layer to a value below 3.2. Also provided is electrical insulation between neighboring devices using the flowable oxide which is cured and annealed. In this case, the annealing can be carried out in hydrogen with or without the presence of aluminum.

Abstract: An object of the present invention is to level out variations in output voltage levels caused by the difference in the characteristics of the output amplifiers of a source driver, and to reduce vertical streak noise on the display screen. A source driver 12 for a liquid crystal panel according to the present invention comprises output amplifier switching means 10 for switching an output amplifier 80, which amplifies analog signal converted from digital image signal by the digital/analog converter 82 and provides the converted analog signal to source lines 74 of a liquid crystal panel 70, to another output amplifier at regular time intervals.

Abstract: A goniometer for performing scanning probe microscopy on a substrate surface is disclosed. The goniometer has a cantilever, having a cantilevered end and a supported end and a tip disposed at the cantilevered end of the cantilever. The goniometer also has a block disposed at the supported end of the cantilever. The block has at least one pair of piezoelectric layers, a pair of electrodes disposed about each individual piezoelectric layer such that varying a potential difference applied between the individual electrodes of a pair of electrodes causes the corresponding piezoelectric layer to deform, and a first insulating material disposed between the individual electrodes for insulating the individual electrodes from each other. The individual piezoelectric layers are deformed at different rates resulting in a deformity of the block and tilting of the cantilever and tip connected therewith.

Abstract: A method to selectively cap interconnects with indium or tin bronzes and copper oxides thereof is provided. The invention also provides the interconnect and copper surfaces so formed.

Abstract: An organic light emitting device has a layer structure having: a first electrode layer; a second electrode layer parallel to the first electrode layer; and, an electrically conductive and light transmissive layer parallel to the second electrode layer. An electrically insulating layer is disposed between the first and second electrode layers. A layer of organic material is disposed between the second electrode layer and the conductive layer. An aperture in the organic layer provides an electrical connection path between the conductive layer and one of the first and second electrode layers.

Abstract: A memory device including at least one pair of spaced apart conductors and a ferroelectric material between the pair of conductors. The pair of conductors is spaced apart a distance sufficient to permit a tunneling current therebetween.

Abstract: Procedures, analysis techniques, and correction methods are presented for assessing the electrical properties of the Si layer of silicon-on-insulator substrates. Detailed analysis and equations are outlined in a computer algorithm written in Mathcad for both the linear and saturated regions of FET behavior.