Patents Represented by Attorney Robinson Intellectual Property Law Office, P.C.
  • Patent number: 8350261
    Abstract: The object is to suppress deterioration in electrical characteristics in a semiconductor device comprising a transistor including an oxide semiconductor layer. In a transistor in which a channel layer is formed using an oxide semiconductor, a p-type silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the p-type silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the p-type silicon layer is not provided.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Hiromichi Godo, Takashi Shimazu
  • Patent number: 8349705
    Abstract: To provide a method of manufacturing a semiconductor device in which the space between semiconductor films transferred at plural locations is narrowed. A first bonding substrate having first projections is attached to a base substrate. Then, the first bonding substrate is separated at the first projections so that first semiconductor films are formed over the base substrate. Next, a second bonding substrate having second projections is attached to the base substrate so that the second projections are placed in regions different from regions where the first semiconductor films are formed. Subsequently, the second bonding substrate is separated at the second projections so that second semiconductor films are formed over the base substrate. In the second bonding substrate, the width of each second projection in a direction (a depth direction) perpendicular to the second bonding substrate is larger than the film thickness of each first semiconductor film formed first.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Tatsuya Mizoi, Hidekazu Miyairi, Koichiro Tanaka
  • Patent number: 8350313
    Abstract: A charge retention characteristic of a nonvolatile memory transistor is improved. A first insulating film that functions as a tunnel insulating film, a charge storage layer, and a second insulating film are sandwiched between a semiconductor substrate and a conductive film. The charge storage layer is formed of two silicon nitride films. A silicon nitride film which is a lower layer is formed using NH3 as a nitrogen source gas by a CVD method and contains a larger number of N—H bonds than the upper layer. A second silicon nitride film which is an upper layer is formed using N2 as a nitrogen source gas by a CVD method and contains a larger number of Si—H bonds than the lower layer.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Nanae Sato
  • Patent number: 8351226
    Abstract: An object of the present invention is to provide a rectifier circuit which can suppress loss of power due to parasitic capacitance or parasitic inductance of a semiconductor element. The rectifier circuit matches or mismatches impedance between a circuit of a previous stage and the rectifier circuit in accordance with the amplitude of an input AC voltage. When an AC voltage to be input has a smaller amplitude than a predetermined voltage, impedance is matched and the AC voltage is applied as is to the rectifier circuit. Conversely, when an AC voltage to be input has a larger amplitude than a predetermined voltage, impedance is mismatched, and the amplitude of the AC voltage is decreased by reflection and then the AC voltage is applied to the rectifier circuit.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takeshi Osada
  • Patent number: 8349671
    Abstract: The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Shinya Sasagawa, Akihiro Ishizuka
  • Patent number: 8352724
    Abstract: The present invention improves efficiency in utilizing grid computing and promotes spread of the grid computing by solving problems of security technology and distributed computer resource management technology. The present invention improves security technology and distributed computer resource management technology that are problems in improving in efficiency and spread of grid computing. Based on an idea that a mechanism for supporting these control technology is required in a microprocessor level, an auxiliary system for supporting security technology and distributed computer resource management is provided in a software area in a microprocessor comprising a hardware area and the software area, according to the present invention.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Akiharu Miyanaga
  • Patent number: 8349702
    Abstract: A semiconductor substrate is provided by a method suitable for mass production. Further, a semiconductor substrate having an excellent characteristic with effective use of resources is provided.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sho Kato, Satoshi Toriumi, Fumito Isaka
  • Patent number: 8349704
    Abstract: A bond substrate is irradiated with accelerated ions to form an embrittled region in the bond substrate; an insulating layer is formed over a surface of the bond substrate or a base substrate; the bond substrate and the base substrate are bonded to each other with the insulating layer interposed therebetween; a region in which the bond substrate and the base substrate are not bonded to each other and which is closed by the bond substrate and the base substrate is formed in parts of the bond substrate and the base substrate; the bond substrate is separated at the embrittled region by heat treatment; and a semiconductor layer is formed over the base substrate.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoki Okuno, Akihisa Shimomura, Hajime Tokunaga
  • Patent number: 8344888
    Abstract: The semiconductor device includes a signal processing circuit, an antenna circuit that is connected to the signal processing circuit, and a storage means that supplies electric power to the signal processing circuit. The signal processing circuit receives and transmits information through the antenna circuit, generates a direct current voltage from signals received by the antenna circuit, and stores the direct current voltage in the storage means. Furthermore, the antenna circuit has an antenna portion that receives signals by an electromagnetic induction method and an antenna portion that receives signals by a microwave method so that signals of frequencies from a wide band can be received. Because signals from a wide band can be received, the environment in which the storage means can be charged is widened.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Osada, Hikaru Tamura
  • Patent number: 8344372
    Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. The increase in the numbers of gate lines and signal lines makes it difficult to mount an IC chip having a driver circuit for driving the gate line and the signal line by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit driving the pixel portion are provided over the same substrate. The pixel portion and at least a part of the driver circuit are formed using thin film transistors in each of which an oxide semiconductor is used. Both the pixel portion and the driver circuit are provided over the same substrate, whereby manufacturing costs are reduced.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 8343799
    Abstract: An object is to manufacture a semiconductor device including an oxide semiconductor at low cost with high productivity in such a manner that a photolithography process is simplified by reducing the number of light-exposure masks. In a method for manufacturing a semiconductor device including a channel-etched inverted-stagger thin film transistor, an oxide semiconductor film and a conductive film are etched using a mask layer formed with the use of a multi-tone mask which is a light-exposure mask through which light is transmitted so as to have a plurality of intensities. The etching step is performed by wet etching in which an etching solution is used.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunichi Ito, Miyuki Hosoba
  • Patent number: 8343847
    Abstract: To prevent, in the case of irradiating a single crystal semiconductor layer with a laser beam, an impurity element from being taken into the single crystal semiconductor layer at the time of laser irradiation.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaki Koyama, Junpei Momo, Eiji Higa, Hiroaki Honda, Tamae Moriwaka, Akihisa Shimomura
  • Patent number: 8343849
    Abstract: To provide a technical means which is capable of increasing crystallinity and planarity of a single crystal semiconductor layer, crystal defects are reduced in such a manner that a single crystal semiconductor substrate, in which an insulating film is formed on its surface and an embrittlement region is formed in a region at a predetermined depth from the surface, and a supporting substrate are attached to each other with the insulating film interposed therebetween; the single crystal semiconductor substrate is separated in the embrittlement region by a heat treatment; a single crystal semiconductor layer is irradiated with laser light over the supporting substrate with the insulating film interposed therebetween; a surface of the single crystal semiconductor layer is etched; and a plasma treatment is performed on the surface of the single crystal semiconductor layer.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata
  • Patent number: 8343858
    Abstract: A method for manufacturing a microcrystalline semiconductor film having high crystallinity is provided. A method for manufacturing a semiconductor device which has favorable electric characteristics with high productivity is provided. After a first microcrystalline semiconductor film is formed over a substrate, treatment for flattening a surface of the first microcrystalline semiconductor film is performed. Then, treatment for removing an amorphous semiconductor region on a surface side of the flattened first microcrystalline semiconductor film is performed so that a second microcrystalline semiconductor film having high crystallinity and flatness is formed. After that, a third microcrystalline semiconductor film is formed over the second microcrystalline semiconductor film.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Tomokazu Yokoi, Koji Dairiki
  • Patent number: 8346497
    Abstract: The invention provides a method for testing a semiconductor film, a manufacturing method of a semiconductor film, a laser crystallization method, a laser crystallization device, and a laser crystallization system, for testing a laser crystallized semiconductor film, which require less time, have sufficient reliability, are excellent in cost management and applicable to mass production. In the method for testing a semiconductor film having an improved crystallinity by irradiating an energy light, the tested semiconductor film is photographed in a dark field digital image and then the luminance of the digital image is calculated by a computer in a constant direction for testing.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Hideyuki Ebine
  • Patent number: 8344387
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 8343816
    Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm?3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Imahayashi, Shinobu Furukawa, Atsuo Isobe, Yasuyuki Arai, Shunpei Yamazaki
  • Patent number: 8343817
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: January 1, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 8338257
    Abstract: An object of the present invention is to provide a nonvolatile semiconductor storage device with a superior charge holding characteristic in which highly-efficient writing is possible at low voltage, and to provide a manufacturing method thereof. The nonvolatile semiconductor storage device includes a semiconductor film having a pair of impurity regions formed apart from each other and a channel formation region provided between the impurity regions; and a first insulating film, a charge accumulating layer, a second insulating film, and a conductive film functioning as a gate electrode layer which are provided over the channel formation region. In the nonvolatile semiconductor storage device, a second barrier formed by the first insulating film against a charge of the charge accumulating layer is higher in energy than a first barrier formed by the first insulating film against a charge of the semiconductor film.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8339828
    Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato