Patents Represented by Attorney Robinson Intellectual Property Law Office, P.C.
  • Patent number: 8330221
    Abstract: It is an object to form single-crystalline semiconductor layers with high mobility over approximately the entire surface of a glass substrate even when the glass substrate is increased in size. A first single-crystalline semiconductor substrate is bonded to a substrate having an insulating surface, the first single-crystalline semiconductor substrate is separated such that a first single-crystalline semiconductor layer is left remaining over the substrate having an insulating surface, a second single-crystalline semiconductor substrate is bonded to the substrate having an insulating surface so as to overlap with at least part of the first single-crystalline semiconductor layer provided over the substrate having an insulating surface, and the second single-crystalline semiconductor substrate is separated such that a second single-crystalline semiconductor layer is left remaining over the substrate having an insulating surface.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Koichiro Tanaka
  • Patent number: 8329536
    Abstract: To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kosei Noda
  • Patent number: 8329520
    Abstract: An island-shaped single crystal semiconductor layer whose top surface has a plane within ±10° from a {211} plane is formed on an insulating surface; a non-single-crystal semiconductor layer is formed in contact with the top surface and a side surface of the single crystal semiconductor layer and on the insulating surface; the non-single-crystal semiconductor layer is irradiated with laser light to melt the non-single-crystal semiconductor layer, and to crystallize the non-single-crystal semiconductor layer formed on the insulating surface with use of the single crystal semiconductor layer as a seed crystal, so that a crystalline semiconductor layer is formed. A semiconductor device having an n-channel transistor and a p-channel transistor formed with use of the crystalline semiconductor layer is provided.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Masahiro Takahashi, Takuya Hirohashi
  • Patent number: 8330249
    Abstract: An object is to provide a semiconductor device mounted with memory which can be driven in the ranges of a current value and a voltage value which can be generated from a wireless signal. Another object is to provide write-once read-many memory to which data can be written anytime after manufacture of a semiconductor device. An antenna, antifuse-type ROM, and a driver circuit are formed over an insulating substrate. Of a pair of electrodes included in the antifuse-type ROM, the other of the pair of the electrodes is also formed through the same step and of the same material as a source electrode and a drain electrode of a transistor included in the driver circuit.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Tokunaga
  • Patent number: 8329506
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Patent number: 8331873
    Abstract: In a semiconductor device which can perform data communication through wireless communication, to suppress transmission and the like of an AC signal, the semiconductor device includes an input circuit to which a radio signal is input, a first circuit, which generates a constant voltage, such as a constant voltage circuit or a limiter circuit, a second circuit to which the generated constant voltage is input and which can change impedance of the semiconductor device, and a filter provided between the first circuit and the second circuit. Transmission of an AC signal is suppressed by the filter, and malfunctions or operation defects such as complete inoperative due to variation in the constant voltage is prevented.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yutaka Shionoiri
  • Patent number: 8330156
    Abstract: In a thin film transistor including an oxide semiconductor, an oxide cluster having higher electrical conductance than the oxide semiconductor layer is formed between the oxide semiconductor layer and a gate insulating layer, whereby field effect mobility of the thin film transistor can be increased and increase of off current can be suppressed.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata
  • Patent number: 8324027
    Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Patent number: 8324079
    Abstract: A semiconductor device in which the damage such as cracks, chinks, or dents caused by external stress is reduced is provided. In addition, the yield of a semiconductor device having a small thickness is increased. The semiconductor device includes a light-transmitting substrate having a stepped side surface, the width of which in a portion above the step and closer to one surface is smaller than that in a portion below the step, a semiconductor element layer provided over the other surface of the light-transmitting substrate, and a stack of a first light-transmitting resin layer and a second light-transmitting resin layer, which covers the one surface and part of the side surface of the light-transmitting substrate. One of the first light-transmitting resin layer and the second light-transmitting resin layer has a chromatic color.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Takahashi, Daiki Yamada, Yohei Monma, Hiroki Adachi, Shunpei Yamazaki
  • Patent number: 8324699
    Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mitsuhiro Ichijo, Kenichi Okazaki, Tetsuhiro Tanaka, Takashi Ohtsuki, Seiji Yasumoto, Shunpei Yamazaki
  • Patent number: 8325526
    Abstract: A semiconductor device is provided, which comprises at least a cell including a plurality of memory elements connected in series. Each of the plurality of memory elements includes a channel formation region, a source and drain regions, a floating gate, and a control gate. Each of the source and drain regions is electrically connected to an erasing line through a semiconductor impurity region.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Aya Miyazaki, Mitsuaki Osame, Hiroyuki Miyake, Shunpei Yamazaki
  • Patent number: 8324693
    Abstract: A thin film transistor of the present invention has an active layer including at least source, drain and channel regions formed on an insulating surface. A high resistivity region is formed between the channel region and each of the source and drain regions. A film capable of trapping positive charges therein is provided on at least the high resistivity region so that N-type conductivity is induced in the high resistivity region. Accordingly, the reliability of N-channel type TFT against hot electrons can be improved.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Satoshi Teramoto
  • Patent number: 8324084
    Abstract: An object is to provide a manufacturing method of a semiconductor substrate provided with a single crystal semiconductor layer with a surface having a high degree of flatness. Another object is to manufacture a semiconductor device with high reliability by using the semiconductor substrate provided with a single crystal semiconductor layer with a high degree of flatness. In a manufacturing process of a semiconductor substrate, a thin embrittled region containing a large crystal defect is formed in a single crystal semiconductor substrate at a predetermined depth by subjecting the single crystal semiconductor substrate to a rare gas ion irradiation step, a laser irradiation step, and a hydrogen ion irradiation step. Then, by performing a separation heating step, a single crystal semiconductor layer that is flatter on a surface side than the embrittled region is transferred to a base substrate.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Junichi Koezuka
  • Patent number: 8326102
    Abstract: The present invention is to provide a beam homogenizer, a laser irradiation apparatus, and a method for manufacturing a semiconductor device, which can suppress the loss of a laser beam and form a beam spot having homogeneous energy distribution constantly on an irradiation surface without being affected by beam parameters of a laser beam. A deflector is provided at an entrance of an optical waveguide or a light pipe used for homogenizing a laser beam emitted from a laser oscillator. A pair of reflection planes of the deflector is provided so as to have a tilt angle to an optical axis of the laser beam, whereby the entrance of the optical waveguide or the light pipe is expanded. Accordingly, the loss of the laser beam can be suppressed. Moreover, by providing an angle adjusting mechanism to the deflector, a beam spot having homogeneous energy distribution can be formed at an exit of the optical waveguide.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hirotada Oishi
  • Patent number: 8325165
    Abstract: Variation occurs in transistor characteristics. The present invention relates to a signal line driver circuit comprising: a plurality of current source circuits corresponding to a plurality of wirings; and a shift register, characterized in that: the plurality of current source circuits each comprise capacitor means for converting a supplied current to a voltage in accordance with a sampling pulse supplied from the shift register and supply means for supplying a current corresponding to the converted voltage.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8324086
    Abstract: An SOI substrate having a single crystal semiconductor layer the surface of which has high planarity is manufactured. A semiconductor substrate is doped with hydrogen to form a damaged region containing a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated to separate the single crystal semiconductor substrate in the damaged region. While a heated high-purity nitrogen gas is sprayed on a separation surface of a single crystal semiconductor layer which is separated from the single crystal semiconductor substrate and irradiation with a microwave is performed from the back side of the supporting substrate, the separation surface is irradiated with a laser beam. The single crystal semiconductor layer is melted by irradiation with the laser beam, so that the surface of the single crystal semiconductor layer is planarized and re-single-crystallization thereof is performed.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Naoki Tsukamoto
  • Patent number: 8325285
    Abstract: A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 4, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hajime Kimura
  • Patent number: 8319215
    Abstract: With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto, Atsushi Umezaki
  • Patent number: 8318588
    Abstract: It is an object of the invention is to provide a method suitable for reprocessing a semiconductor substrate having favorable planarity. Another object of the invention is to manufacture a reprocessed semiconductor substrate by using the method suitable for reprocessing a semiconductor substrate having favorable planarity, and to manufacture an SOI substrate by using the reprocessed semiconductor substrate. A projecting portion of a semiconductor substrate is removed using a method capable of selectively removing a semiconductor region which is damaged by ion irradiation or the like. Further, an oxide film is formed on a surface of the semiconductor substrate when the semiconductor substrate is planarized by a polishing treatment typified by a CMP method, whereby the semiconductor substrate is evenly polished at a uniform rate. Moreover, a reprocessed semiconductor substrate is manufactured using the aforementioned method, and an SOI substrate is manufactured using the reprocessed semiconductor substrate.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Imahayashi, Hideto Ohnuma
  • Patent number: 8319641
    Abstract: The object of the present invention is to provide an article management method by which detecting the location of an object is performed easily and introduction costs for detecting the location of an object are suppressed. The article management method includes a first RF chip attached to an article, a first reader/writer into which a shared memory portion and a second RF chip are incorporated, and a second reader/writer. The first reader/writer obtains information stored in the first RF chip, the shared memory portion retains the obtained information about the first RF chip, the second RF chip reads out that information about the first RF chip stored in the shared memory portion, the second reader/writer, by the second RF chip, obtains the information about the first RF chip and information stored in the second RF chip and information about the location of the second RF chip.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: November 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa