Abstract: A method of selecting an intermediate frequency (fIF) is disclosed (FIG. 7). The method includes measuring a first signal quality (704) on a first channel at a first intermediate frequency. The method further includes measuring a second signal quality (706) on the first channel at a second intermediate frequency. The intermediate frequency with the best signal quality is selected (710).

Abstract: In at least some embodiments, an electronic device comprises a processor and an encryption/decryption (E/D) engine coupled to the processor via a bus. The E/D engine selectively operates in a first mode and a second mode. For the first mode, an E/D engine output is provided to the bus. For the second mode, the E/D engine output is not provided to the bus and is accessible only to the E/D engine.

Abstract: A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (gm) than if a single transistor were used while maintaining the same loop bandwidth and drain-to-source current through the transistor. As a result of a smaller transconductance in the VCO, a larger resistor can be used in the loop filter without increasing the noise. With a larger resistor, a smaller capacitor can be used in the loop filter as well. Alternatively, the transconductance can be reduced by a certain factor and the resistance value can be increased by the same factor to maintain a constant loop bandwidth but with a reduction in the amplitude of the noise. Thus, a smaller loop filter capacitor can be achieved albeit with the same noise level, or a lower noise level with the same size capacitor for the loop filter.

Abstract: A transmission of information between a secondary to a primary node in a wireless network occurs in a plurality of N logical time durations. Bundled feedback information for multiple DL transmissions is provided in one UL transmission. Each DL transmission is indicated by a DL grant comprising an M-bit downlink assignment indicator (DAI) field. The primary node increments the value of the M-bit DAI field in successively transmitted DL grants. The secondary node examines the value of the M-bit DAI field in received DL grants, to determine the bundled feedback information.

Abstract: A method of achieving reduced modulation range requirement in a Digitally Controlled Oscillator (DCO) which is deployed as part of a DRP (Digital Radio Processor) and tuned to a tuning frequency range having operating-channel center-frequencies, wherein phase difference between consecutive samples is termed as FCW (Frequency Control Word), uses the steps of digitally modifying and limiting the FCW so that the FCW does not exceed known FCW thresholds, e.g., chosen from ?/2, ?/4, ?/8, and redistributing the FCWs while maintaining a cumulative sum of phases and without significant EVM (Error Vector Magnitude) degradation. The FCW threshold can be chosen arbitrarily and need not be in the form of ?/2n. The method uses a FCW limiting algorithm which reduces supply voltage sensitivity of the DCO and enables significant reduction in area of capacitor bank which would be otherwise needed.

Abstract: A method and system of performing thread scheduling. At least some of the illustrative embodiments are computer-readable mediums storing a program that, when executed by a processor of a host system, causes the processor to instantiate a CPU object that represents a processor abstraction, create a CPU context object that represents a thread abstraction (wherein the CPU context object is associated to a method, and wherein the CPU context object is mapped onto the CPU object), and execute the method within the CPU object.

Abstract: This invention is a method of wireless communication having a communications protocol providing more downlink subframes than uplink subframes. The user equipment transmits a combination of a plurality of ACK/NAK response signals and related data. The related data could be the number of bits N of the plurality of ACK/NAK response signals or the number of detected downlink communications grants S requiring ACK/NAK response signals. This related data could be a cyclical redundancy check set of bits which may be scrambled upon the numbers N or S. Similar selections are feasible with resource elements or an index of a modulation symbol or codeword.

Abstract: This invention is a transmission scheme for multi-ACK/NAK and SRI in TDD. The described scheme enables using DAI as pure counter. QPSK is adopted as the modulation scheme in this invention which guarantees satisfactory detection performance. Link level simulations show that the event of one DL grant pass followed by three consecutive DL grant misses is of low probability.

Abstract: A method, system, and apparatus of a DC current based on chip RF power detection scheme for a power amplifier are disclosed. In one embodiment, a method includes generating a scaled current from an other current associated with power amplifier, transforming the scaled current (e.g., the scaled current may be scaled to the other current value) into a digital signal and using the digital signal to set a radio frequency power value of an antenna of the antenna module. The method may include transforming the scaled current into a voltage signal. The method may also include transforming the voltage signal into the digital signal. The method may also include generating a current mirror from a low dropout regulator.

Abstract: A communication device adjusts its power level based on a desired quality of service and based on a data rate being used to transmit data. The communication device may comprise a processor, a transceiver, and a power source that provides a power level to the transceiver for transmitting data at a variable rate. The processor obtains a first value indicative of a number of transmission errors, computes a second value using the first value and based on the data rate, and determines whether the second value is below a threshold. Based on a comparison of the second value to said threshold, the processor initiates a change in the power level. Additionally or alternatively, the processor may adjust the power level based on whether a current frame contains an error, but not permitting the power level to be decreased to a level at which a signal-to-interference ratio falls below a threshold.

Abstract: Transmission of information between user equipment (UE) and base stations in a wireless network occurs using a stream of periodic data. A modem in the UE operates synchronized to a first clock source to produce the stream of periodic data at a chip rate. Transceiver circuitry is synchronized to a variable clock source to receive the stream of data from the first circuitry at a rate according to the variable clock source. A fixed phase relationship is maintained between the variable clock source and the first clock source while the data period is uniform by adjusting the variable clock in response to detected phase errors. Occasionally, one period of the periodic data is changed by a defined amount. The fixed phase relationship is restored over a number of periods in a gradual manner by changing the frequency of the variable clock by an amount. By restoring the phase relationship gradually, quality degradation of the transmitted signal is reduced.

Abstract: In a method for tracing data within an integrated circuit, a default time stamp granularity is selected for a sequence of time stamps, wherein each time stamp has a resolution of 2**N. A sequence of trace events is captured and an elapsed time is determined between each time sequential pair of trace events in the sequence of trace events. A time stamp is formed to associate with each trace event of the sequence of trace events, wherein each time stamp has an associated time stamp granularity, wherein the time stamp has the default time stamp granularity if the elapsed time between a current trace event and a sequentially prior trace event is less than 2**N time slots, otherwise the time stamp granularity is slid to a larger value such that the elapsed time can be represented by N bits, whereby a small number N of bits can accurately represent a large range of elapsed times.

Abstract: A system-on-chip (SOC) that includes a plurality of initiator components, and a target memory component coupled to the initiator components and having a target firewall, wherein the target firewall is configured to be programmed with a data structure which indicates, for at least one portion of the target memory component, access conditions for each initiator component.

Abstract: System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.

Abstract: A method is described for simulating the f-sigma timing path delay of an integrated circuit design when local transistor variations determine the stochastic delay. This is achieved by determining an estimated delay time for a first timing path using non-linear operating point analysis of local variations (NLOPALV). An operating point is calculated for each cell that is included in a timing path in the integrated circuit design. The f-sigma operating point of a cell-arc is a point on the cell-arc delay function (CADF). An f-sigma delay value is determined for each cell using the selected operating point on the CADF of the cell. The determined delay values of the plurality of cells in the timing path may then be combined to predict the estimated delay for the entire timing path. The method may be extended to deal with slew rate, predict hold time statistics, prune paths, and deal with convergent paths.

Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.

Abstract: A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward unit processes a signal for transmission, a feedback unit coupled to the feed forward unit, the feedback unit generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit, a closed loop power control unit coupled to the feedback unit and to the feed forward unit, the closed loop power control unit generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source or software instructions, and a ramp path power control unit coupled to the data source, the ramp path power control unit generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: Aspects of the present invention provide a system and method for checking a portion of an analog circuit using a digital checker. The method includes establishing a target in the analog circuit, creating an analog target dummy for the target, creating a digital target dummy, binding the digital target dummy to the analog target dummy, and checking a value of the digital target dummy with a digital checker.

Abstract: Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises: receiving a signal containing first portions that are based on known data and second portions that are based on unknown data; generating a training signal, from the received signal, that substantially represents one or more of the first portions; adapting filter coefficients using the training signal; and equalizing the received signal using the adapted filter coefficients.

Abstract: A method of wireless handover in a broadcast network (FIGS. 5 and 8) is disclosed. A wireless receiver (FIG. 4) receives a first signal (N) from a first transmitter (f1). The receiver measures a signal strength (RSSI) of the first signal. The strength of the first signal is compared to a first threshold (T0). The receiver receives a second signal (N+3) from a second transmitter (f3) in response to the step of comparing. The first and the second signals are sent to an application processor (120). The wireless receiver continues to receive the first and second signals until the application processor terminates receiving one of the first and second signals.