Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

Abstract: A Hybrid Automatic Retransmission Request (H-ARQ) technique is provided for Multi-Input Multi-Output (MIMO) systems. The technique changes the basis (V) upon retransmission, which helps reduce the error probability upon retransmission. This basis hopping technique provides for improved performance gain without significant increase in design complexity. In one embodiment, communication device (100) includes a receiver section (114) for receiving an acknowledgment (ACK) or a non-acknowledgment (NACK) signal in response to information transmitted by the transmitter section of the communication device. If a NACK is received, a new basis is selected from a set of basis stored in a basis set unit (110). The new basis that is selected is then used by a linear transformation unit (106) in the retransmission of the information.

Abstract: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.

Abstract: According to an aspect of the present invention, each correlation block in a Global Navigation Satellite System (GNSS) receiver is designed to examine a certain number of consecutive samples of an input signal and a buffer is designed to store more than such number of samples. Due to such storing, each correlator may perform multiple correlations for the same set of received samples. According to another aspect, such searches may be performed without rotating a local code by controlling the specific samples provided as window samples. Thus, while performing Doppler searches, different frequencies can be searched using the same local code without rotation. While performing code phase searches, the window samples may start from different positions with the position determining the specific phase being searched.

Abstract: A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp.

Abstract: A novel and useful mechanism for reducing the required backoff and the peak to average power ratio (PAPR) needed for an OFDM transmitter whiles still meeting spectral mask and EVM specifications. The mechanism searches, for each packet to be transmitted, for several possible scrambler and encryption sequences that would yield the best spectral mask and EVM with lowest PAPR. The search can be performed using the existing transmitter and receiver PHY circuit chain to modulate and demodulate the candidate hypotheses. Once the scrambler sequence and/or encryption sequence is selected, the packet is transmitted using the selected scrambler and encryption sequences. In addition, the invention exploits the fact that even for very low backoff margins, a reduced number of candidate hypotheses may be tested while still yielding a high probability of meet the spectral mask and EVM specifications.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: A system and method for controlling a telecommunications device capable of text telephone, and voice carry over or hearing carry over operation where transition from text to voice operation, and vice versa, is accomplished without operator intervention. The system includes a text telephone signal detector that detects the presence of text telephone signals and an audio control manager coupled to the text telephone signal detector. The audio control manager comprises an audio stream manger that controls the processing of audio signals, and an audio profile manager that controls the routing of voice signals to the audio peripherals and the audio peripheral output sound loudness.

Abstract: A method and system for implementing a micro-sequence based security model in a processor. More particularly, micro-sequences and JSM hardware resources are employed to construct a security model invisible to applications, and when memory constraints are in place, extend a complex security model in JSM code by implementing a micro-sequence security trigger. The method includes micro-sequence based security policy that determines whether an instruction accesses a privileged resource associated with a processor and when not already in privilege mode and not executing a micro-sequence, the micro-sequence based security policy is applied to the instruction to control access to the privileged resource according to the security policy.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter for use in a base station of an OFDMA system and includes a primary module configured to provide a primary synchronization signal that furnishes a partial cell identity. Additionally, the transmitter also includes a secondary module configured to provide a secondary synchronization signal that furnishes a cell identity group and one or more cell-specific parameters based on using a two-segment secondary synchronization sequence. The transmitter further includes a transmit module configured to transmit the primary and secondary synchronization signals.

Abstract: Instantiating a plurality of buffers in a random access memory by storing in the random access memory (RAM) a plurality of descriptors each containing a base address, at least one address pointer and a size to define a corresponding one of the plurality of buffers. Transferring data in any one of the plurality of buffers by using a control function within an accessing module to generate a buffer address by accessing and updating the address pointer in the corresponding descriptor. In a processor that accesses the circular buffers, the control function is one or more complex instructions tailored for computing read and write addresses to access the circular buffer using fields within the corresponding descriptor. In a DMA module that accesses the circular buffers, the control function is a hardware controller that computes read and write addresses using the fields within the corresponding descriptor to access the circular buffer.

Abstract: A ring oscillator has at least one latch connected to the outputs of at least one oscillator stage, where the latch drives the outputs of the oscillator stage to opposite states during startup, and drive strength reduction circuitry to reduce drive strength of the latch after startup when the oscillator is oscillating.

Abstract: A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. The system also comprises security logic coupled to the control logic and adapted to restrict usage of the system if the control logic attempts to fetch an instruction op-code from the stack.

Abstract: A processor executes an instruction that causes a comparison to be performed between contents of a first register and contents of a second register and between the contents of the first register and a predetermined value. The instruction is particularly useful for determining whether an attempted access (either a load or write) to an array improperly targets a location outside the boundary of the array. In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.

Abstract: A tactile input to a system having a speaker located in an enclosure with an audio port can be detected by generating a sound wave in response to a signal and sensing the phase relationship between the current phase and the voltage phase of the signal. While the audio port is open a baseline current and voltage phase difference is established. When the audio port is obstructed by a finger touch, the current and voltage phase difference is altered in response to the obstruction. While the altered phase difference is detected, a tactile event is indicated.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter is for use with a base station in a in a cellular communication system and includes a scheduling unit configured to provide a primary synchronization signal selected from a group of multiple sequences, wherein at least two of the sequences have complex conjugate symmetry in the time domain. The transmitter also includes a transmit unit configured to transmit the primary synchronization signal. Additionally, the receiver includes a receive unit configured to receive a primary synchronization signal. The receiver also includes a detection unit configured to identify one of a plurality of primary synchronization signals corresponding to a communication cell location of the receiver, wherein at least two of a group of multiple sequences have complex conjugate symmetry in the time domain.

Abstract: A digital communications system for delivering data blocks includes at least one transmit/receive unit (TRU). The TRU includes a storage element for receiving transmit data packets and retransmit data packets from a sending unit and a processing element communicatively coupled to the storage element. The processing element is configured for recognizing a failure to receive at least one other transmit data packet (missing data packet) from the sending unit, and for configuring a status control packet for transmission to the sending unit, the control packet includes a header including a next packet identifier for a next data packet anticipated to be received and a status payload portion including a missing packet identifier including the transmit packet identifier for the missing data packet. In the system, the retransmit data packet includes at least a segment of the data payload in the missing data packet associated with the missing packet identifier.

Abstract: A wireless communications network, including a base station (10) and wireless units (UE), is disclosed. The wireless units (UE) request a connection with the base station (10) by the transmission of a preamble within time slots designated by the base station (10). The disclosed preambles are Walsh Hadamard code symbols, repeated a number of times so as to have the same length as a cell-specific scrambling code. The wireless unit (UE) requesting a connection pseudo-randomly selects a time slot from those available, and one of the Walsh Hadamard code symbols, replicates the code symbol into a spread interleaved bitstream, scrambles this bitstream and transmits it to the base station (10). Upon receipt, the base station (10) applies the incoming bitstream to a matched filter (98) to descramble the signal, following which the symbol is de-interleaved by way of a sequence of delay lines (100).

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: A method of compression of videotelephony images characterized by: creating (10) a learning base containing images; centering the learning base about zero; determining component images by principal component analysis (12); and keeping a number of significant principal components (14).