Patents Represented by Attorney, Agent or Law Firm Ronald P. Kananen, Esq.
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Patent number: 6545546Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.Type: GrantFiled: October 18, 2001Date of Patent: April 8, 2003Assignee: Sony CorporationInventors: Toru Takeshita, Takashi Nishimura
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Patent number: 6541345Abstract: Disclosed is a semiconductor device including a SOI substrate having a SOI layer, in which a structure made from a semiconductor device is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer dielectric film and including at least a connection hole positioned on the region in which the contact is to be formed. With this semiconductor device, a contact reaching a back gate electrode can be formed without increasing an aspect ratio of the contact even when a thick oxide film is grown on the back gate electrode in the filed area by selectively oxidizing the back gate electrode in the field area.Type: GrantFiled: May 4, 1998Date of Patent: April 1, 2003Assignee: Sony CorporationInventor: Hiroshi Komatsu
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Patent number: 6541922Abstract: An alternating current driven type plasma display device having (a) a first panel comprising a first substrate; a first electrode group constituted of a plurality of first electrodes formed on the first substrate and a protective layer formed on the first electrode group and on the first substrate and (b) a second panel comprising a second substrate fluorescence layers formed on or above the second substrate; and separation walls which extend in the direction making a predetermined angle with the extending direction of the first electrodes and each of which is formed between one fluorescence layer and another neighboring fluorescence layer, wherein discharge is caused between each pair of the first electrodes facing each other, and a recess is formed in the first substrate between each pair of the facing first electrodes.Type: GrantFiled: December 29, 2000Date of Patent: April 1, 2003Assignee: Sony CorporationInventor: Shinichiro Shirozu
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Patent number: 6541326Abstract: A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating film and gate electrode stacked on a channel forming region of a semiconductor provided on the surface of a substrate and planarly dispersed charge storing means such as carrier traps in a nitride film or near the interface with the top insulating film, provided in the gate insulating film, the gate insulating film including an FN tunnel film having a dielectric constant larger than that of a silicon oxide film and exhibiting an FN electroconductivity, whereby the thickness of the gate insulating film, converted to that of a silicon oxide film, can be reduced and the voltage can be reduced.Type: GrantFiled: April 6, 2001Date of Patent: April 1, 2003Assignee: Sony CorporationInventor: Ichiro Fujiwara
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Patent number: 6541913Abstract: In a flat display device, display can be carried out with high definition and high density, and furthermore, driving power, that is, consumed power can be reduced. First and second substrates 1 and 2 are provided opposite to each other, the first substrate 1 is provided with a discharge maintaining electrode group 5 having a plurality of discharge maintaining electrodes 3 and 4 arranged thereon, and the second substrate 2 is provided with an address electrode group 9 having a plurality of address electrodes 8 arranged thereon. The discharge display is carried out through negative glow discharge and cathode glow discharge.Type: GrantFiled: June 29, 2000Date of Patent: April 1, 2003Assignee: Sony CorporationInventors: Hiroshi Mori, Hidehiro Kawaguchi
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Patent number: 6538370Abstract: A cathode-ray tube electron gun can alleviate unwanted radiation caused when cathodes and a first electron gun constitute an antenna by increasing the number of conduction leads of a first electrode of a cathode-ray tube electron gun from one to a plurality of conduction leads.Type: GrantFiled: July 27, 1999Date of Patent: March 25, 2003Assignee: Sony CorporationInventors: Yasunobu Amano, Norifumi Kikuchi, Takashi Shirai, Motomu Tadama, Kazuo Sugimoto, Mitsunori Endou
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Patent number: 6539529Abstract: Disclosed are a method and an apparatus for designing an integrated circuit, as well as a storage medium for storing the method, whereby repeaters are laid out automatically without overlapping with existing circuit blocks. A set of layout data is input to let the repeaters fully occupy provisionally regions that are free of circuit blocks and ready to accommodate the repeaters. Another set of layout data is generated based on the input layout data to calculate locations in which to insert the repeaters within wiring patterns that fail to meet wiring delay requirements. From among the provisionally laid-out repeaters, those that are closest to the calculated positions are selected. Data about connections of the selected repeaters are added to a net list to update the latter. Data about the layout of the unselected repeaters are removed from the layout data in effect after the provisional layout.Type: GrantFiled: October 25, 2001Date of Patent: March 25, 2003Assignee: Sony CorporationInventors: Motoji Ebisawa, Arata Yamamoto, Ryouhei Inoue
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Patent number: 6536136Abstract: To provide a substrate transfer apparatus capable of forming a hermetically-closed space integrated between a normal substrate processing apparatus which is not integrated with a substrate transfer unit and a substrate transfer container, the substrate transfer apparatus includes a main body in a box-like shape containing a substrate W, an upper opening (first opening) provided at the main body and connected to a bottom opening (substrate transfer port) of a container while maintaining an air tight state against outside air, a side wall opening (second opening) provided at the main body and connected to a substrate transfer port of the transfer processing apparatus while maintaining the air tight state against outside air, an exhaust pipe connected to the main body, an opening/closing mechanism for opening and closing a bottom lid relative to the bottom opening in a state in which the upper opening and the bottom opening of the container are connected and transfer mechanisms installed in the main body for traType: GrantFiled: January 26, 2001Date of Patent: March 25, 2003Assignee: Sony CorporationInventor: Koichiro Saga
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Patent number: 6533473Abstract: An imaging apparatus with an exposure controlling mechanism being made to define an iris aperture by moving iris blades on surfaces perpendicular to an optical axis, wherein the exposure controlling mechanism includes a first iris blade to which a first ND filter having at least two levels of transmissivity is attached, a second iris blade to which no ND filter is attached, and a third iris blade to which a second ND filter having a single transmissivity is attached, and the first to the third iris blades are made to differ respectively in amounts and phases of their displacements caused by an operation of a driving means.Type: GrantFiled: October 20, 2000Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Toshiaki Edamitsu, Yusuke Nanjo, Keisuke Ikegami, Yuichi Nakano
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Patent number: 6534812Abstract: A memory cell with a stored charge on its gate comprising; (A) a channel forming region, (B) a first gate formed on an insulation layer formed on the surface of the channel forming region, the first gate and the channel forming region facing each other through the insulation layer, (C) a second gate capacitively coupled with the first gate, (D) source/drain regions formed in contact with the channel forming region, one source/drain region being spaced from the other, (E) a first non-linear resistance element having two ends, one end being connected to the first gate, and (F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.Type: GrantFiled: January 19, 2000Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Mikio Mukai, Yutaka Hayashi
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Patent number: 6535255Abstract: An illumination intensity correcting circuit including a curve fitting circuit formed by differential amplifier circuits and a load resistor, wherein the amplification factor of the curve fitting circuit is changed before and after each breakpoint voltage, the reference voltages of the differential amplifier circuits are set so that at least two breakpoint voltages are arranged in the range of a voltage of a video signal, and the amplification factors of the differential amplifier circuits are set so that the amplification factor of the curve fitting circuit in the range of the signal voltage inside of the two breakpoint voltages is smaller than the amplification factor outside of the two breakpoint voltages.Type: GrantFiled: September 25, 2001Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Hitoshi Motonakano, Shozo Mitarai, Akira Arimizu
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Patent number: 6533000Abstract: A hermetic substrate transportation container permitting storage of an electronic substrate is provided, keeping a rise of internal moisture concentration low, thus preventing generation of natural oxidation film on the surface of the electronic substrate and allowing detection of the contents inside the substrate transportation container, from outside. A container body having an aperture for loading and unloading an electronic substrate, the substrate transportation container comprising a lid for sealing such aperture, in which the container body and the lid are made of a material having an amorphous polyolefin as its main constituent. By constituting the container body and the lid using the amorphous polyolefin with low hygroscopic characteristic as a main constituent, it is possible to keep discharge of moisture from the internal wall thereof low and also to prevent an increase of moisture concentration in the sealed compartment.Type: GrantFiled: April 11, 2001Date of Patent: March 18, 2003Assignee: Sony CorporationInventor: Koichiro Saga
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Patent number: 6536013Abstract: The present invention clarifies the conditions for the required element techniques to be technically superior and makes it easy to establish the development guideline during the development of a memory embedded semiconductor integrated circuit. The total resource CW of a fabrication technique is defined by utilizing the process number or mask number, etc.Type: GrantFiled: December 7, 2000Date of Patent: March 18, 2003Assignee: Sony CorporationInventors: Toshio Kobayashi, Naoshi Ikeda
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Patent number: 6532165Abstract: In NAND type nonvolatile semiconductor memory each memory cell is made of a dual gate transistor connected at one gate portion thereof to ferroelectrics, a plurality of such memory cells are connected in series to form a memory block, and a plurality of such memory blocks are arranged to form a memory cell array and make up NAND type nonvolatile semiconductor memory. Used as each dual gate transistor is a thin film transistor which has a first gate formed on one surface of a semiconductor thin film via a first gate insulating film and a ferroelectric thin film, and a second gate electrode formed on the other surface of the semiconductor thin film via second gate insulating film in confrontation with the first gate electrode. Alternatively, ferroelectric gate type dual gate thin film transistors are made by forming thin film transistors on opposite surfaces of a ferroelectric thin film to form memory cells.Type: GrantFiled: May 30, 2000Date of Patent: March 11, 2003Assignee: Sony CorporationInventor: Kenji Katori
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Patent number: 6531334Abstract: A hollow package includes a package body composed of an epoxy resin having a low thermal coefficient of linear expansion, wherein the package body includes a recess for receiving an electronic component, and leads, for extracting electrodes of the electronic component, extending from the inner surface of the recess, via the upper surface of the package body, to the peripheral surface, and a transparent sealing plate bonded onto the upper surface of the package body with an ultraviolet-curable resin.Type: GrantFiled: November 2, 2001Date of Patent: March 11, 2003Assignee: Sony CorporationInventor: Keiji Sasano
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Patent number: 6532592Abstract: A bi-directional communications link between a television set and a remote control unit assists a viewer in controlling the entertainment system. The television set can signal the remote control unit to confirm instruction signal received from the remote control unit. The television can also transmit electronic program guide information to the remote control unit which is displayed on a display device on the remote control unit. The television can send the remote control unit a listing of available sub-channels within a single digital channel. The listing is displayed on the remote's display device, and the viewer can then choose from among the sub-channels.Type: GrantFiled: November 9, 1998Date of Patent: March 11, 2003Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: Peter Rae Shintani, Hirofumi Usui
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Patent number: 6529454Abstract: A cylindrical lens 39 for generating focussing error signals is formed as one with a portion of an optical component 33 of a transparent material lying on an optical path L2 that is an optical path of a return light beam from the optical member 33. This configuration assures a small size while reducing the production cost and improving operational reliability.Type: GrantFiled: March 8, 2000Date of Patent: March 4, 2003Assignee: Sony CorporationInventors: Yoshito Asoma, Kiyoshi Toyota, Noriaki Nishi
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Patent number: 6525947Abstract: Providing a power supply system having a plurality of power supply apparatuses connected in parallel to each other, each of which is not affected by a voltage fluctuation of a reverse flow-preventive diode provided in an output line thereof, and can provide a stable output voltage controlled with high accuracy. Each of the power supply apparatuses includes a positive output terminal 33 connected to a load 13, a reverse flow-preventive diode 31 connected to the positive output terminal 33, a VF correcting circuit 46 for detecting a forward voltage of the reverse flow-preventive diode 31 and providing a controlling unit with the detected voltage in a feedback manner, an output current detecting/correcting circuit 45 for detecting a forward current of the reverse flow-preventive diode 31 and providing the controlling unit with the detected current in a feedback manner, and the controlling unit for controlling the anode potential of the reverse flow-preventive diode 31.Type: GrantFiled: July 25, 2001Date of Patent: February 25, 2003Assignee: Sony CorporationInventors: Koji Umetsu, Masayoshi Sasaki
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Patent number: 6525787Abstract: A liquid crystal panel and a liquid crystal projection display apparatus comprising the liquid crystal panel, the liquid crystal panel comprising an insulating substrate, plural pixel electrode formed above said insulating substrate, plural thin film transistors each driving each of said pixel electrode, and a light-shielding layer formed between said thin film transistor and said insulating substrate.Type: GrantFiled: September 11, 1998Date of Patent: February 25, 2003Assignee: Sony CorporationInventor: Takusei Sato
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Patent number: 6525770Abstract: The initial value T0 of the period of a four-phase driving signal for driving a CCD of an image pickup device is calculated according to the equation T0=(L×p)/(f×v). Wherein, L represents the distance from the CCD to a product (object), if represents the focus length of the optical system used between the CCD and product, v represents the transferring speed of the product, and p represents the distance interval of photodiodes of the CCD. Afterward, the period T of the driving signal is adjusted properly depending on the pickup position of the product. Because electric charges corresponding to the same portion of the image of the product are accumulated in the same potential well formed by the driving signal by generating the driving signal as described above, the image of the product is picked up with suppressed blurring regardless of the speed of the product. Blurring is prevented during image pickup of an transferring object by the method described above.Type: GrantFiled: January 29, 1998Date of Patent: February 25, 2003Assignee: Sony CorporationInventors: Kuzuhiko Ueda, Takeshi Kubozono