Abstract: The present disclosure is directed to an arrangement whereby any one of a plurality of different or similar interface circuit cards can be located into any one of a number of slots or holding means of a data processing system, without preassignment thereto, and whereby each of the interface circuit cards will generate its own diagnostic routine signals and signals representing its own identification, the latter signals being used in a self-configuration operation of the system and whereby an arbiter means is employed to determine, among the plurality of interface circuits, which has the highest priority in the event more than one of said interface circuits is requesting the use of a common data flow path.

Abstract: The present system employs a high speed digital signal processor which is programmed to generate pairs of digitized waveforms, each pair representing a pair of different frequencies in response to coded input signals. Each pair of different digitized waveforms, when converted and combined into an analog signal, represents a "tone pair" as used in major telephone systems. The tone pairs are transmitted through an anti-aliasing filter circuit and therefrom through amplification circuitry to a tone pair decoder of the type used in major telephone systems. At the tone pair decoder the tone pair signals are reconverted into binary signals. The binary signals from the tone pair decoder are transmitted to a data processor in the system under test, whereat they may or may not be further decoded. Ultimately the binary signals are compared with the coded input signals originally sent.

Abstract: Device for detecting the direction and change of rotational speed of a rotating element. In one embodiment, a pair of phototransistors which are energized by a light source according to an ordered sequence through a disk formed by opaque and transparent sectors coupled to the rotating element. The two phototransistors controls, when energized the switching on of two transistors which enable the discharge of two capacitors, charging with a predetermined time constant in the interval time between discharges. The discharge control action of one of the two phototransistors on a first capacitance is however conditioned by the charge level reached by the other capacitance and therefore both by the order in which phototransistors are energized and by the energization frequency. If the energization frequency is lower than a certain limit or the energization order is not the correct one, the first capacitor reaches a charge level higher than a reference value and supplies an indication signal accordingly.

Abstract: In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

Abstract: A microprogrammed data processing system includes a cache memory, a decimal unit and an execution unit. The decimal unit receives operands from cache memory, strips the non-decimal digit information from the operands, and assembles the 4-bit decimal digits from the operand into words containing a maximum of 8 decimal digits for transfer to the execution unit. The execution unit processes the words in accordance with a decimal numeric instruction. The throughput of the system is increased when processing short operands which contain 15 decimal digits or less by apparatus in the decimal unit which detects the short operand and determines the number of cache memory cycles between the cycle the first word of the short operand is received from cache memory and the cycle on which the first assembled word is transferred to the execution unit for processing.

Abstract: Mantissa results of floating point operations are truncated to words of 24 bits each by storing the 64 bit mantissa result in a first address location of a random access memory, and storing binary ZEROs in the 48 least significant bit positions of a second address location of the random access memory. The mantissa result is truncated by addressing the high order 24 bits at the first address location and the 48 binary ZEROs at the second address location.

Abstract: A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory locations corresponding to a predetermined increment of memory capacity. The board includes a set of switches whose input terminals are connected to receive predetermined ones of a plurality of address signals. These predetermined signals are coded specifying the segments of memory being accessed. The signals applied to the switch output terminals are logically combined and the resulting signal is applied to a group of memory present circuits connected to receive other ones of the address signals representative of the row of chips being addressed.

Abstract: Multiple common buses are provided for coupling a plurality of units in a data processing system for the transfer of information therebetween. The central processing unit (CPU) allocates the multiple common buses to one of the units in response to bus requests received from various units desiring to use the common buses. Bus requests are generated in a synchronous manner by use of a timing signal originating in the CPU which is connected in series between the one or more units on each of the multiple common buses.

Abstract: Apparatus for use in coupling an automated maintenance system of general utility to a central processing unit of a data processing system. The interface apparatus is comprised of path control and operational condition control registers to control and enable the paths accessed by the automated maintenance system and to control the conditions of operation of the central processing unit. A control point register stores control point information from the central processing unit indicating its internal status. This information is read and displayed by the automated maintenance system. Address and data registers serve to buffer data and addresses exchanged between the automated maintenance system and the CPU. The disclosed interface apparatus allows a general utility automated maintenance system to be adapted to test a specific central processing unit.

Abstract: Digital data is recorded on the surface of a magnetic media such as a disk or diskette in the form of magnetic flux transitions identifying clock and data information in a modified frequency modulation (MFM) mode. A read head senses the flux transitions which are in turn converted to digital signals. A counter in the adapter starts to count when the adapter receives a digital signal. The count is transferred to a register and the counter presets when the adapter receives the next digital signal. The count is indicative of the time between the successive digital signals and should be representative of multiples of an integer. The count signals stored in the register address a read only memory whose output signals preset the counter to a value to compensate for the difference between the expected time and the actual time between the successive digital signals thereby reducing the read error rate.

Abstract: A data mover for moving blocks of data stored in a first location of the working store of a data processing system to a second location in the working store. The data mover is provided with the necessary registers, switches, counters and control circuits to issue read and write commands to the working store, to receive and store in registers data read out of the working store as the result of its having issued a read command, and to write data read out of working store and stored in its registers in response to a read command issued by the data mover into another location in the working store. These steps are repeated until a block, measured in thousands, of data words has been moved from the first to the second location. The address preparation circuits of the high speed multiplexer of the data processing system through which the data mover communicates with the working store of the system is used to provide a substitute memory command for one of the two types of memory commands issued by the data mover.

Abstract: If the firmware calls for an operand rounding operation, apparatus in the Scientific Instruction Processor (SIP) tests the bit to the right of the low order bit of the normalized operand to determine if a rounding cycle is required. If the operand requires a normalization cycle or a mantissa overflow correction cycle, the rounding operation is performed in those cycles.

Abstract: A Scientific Instruction Processor (SIP) uses a Programmable Read Only Memory (PROM) to control the output of a two stage shifter. The shifter performs the necessary mantissa shift operations of shift right, shift left, shift right around, as well as inserting certain constant information into the system. Control signals and shift signals applied to the input address terminals of the PROM select the PROM output signals which enable the selected mantissa hexadecimal digits which output the shifter. This forces hexadecimal digits from the enabled positions and hexadecimal ZERO digits in those positions not enabled.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

Abstract: In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.