Abstract: In a microprogrammed data processing system, the throughput of the system is increased by apparatus which counts the number of leading zero digits of an operand on the cycle in which the operand word is processed through the decimal unit and sends that count to the execution unit in response to a predetermined microword.The apparatus counts the number of leading zero digits by first storing in a register the number of words the decimal unit will not send for processing as determined by an instruction descriptor. As the operand is received by the decimal unit, most significant word first, the number of leading zero digits in the operand is added to the register on the same cycle the operand word is processed through the decimal unit, thereby generating a count of the number of zero digits in the operand that the decimal unit will send for processing. This leading zero digit count is available to the firmware in response to a microword command.

Abstract: In a microprogrammed data processing system the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which indicates to the microprogram the characteristics of the operand being processed. This enables the proper microprogram subroutine; that is, if the operand is a floating point or a scaled number, has 4-bit decimal digits or 9-bit decimal digits, has an overpunched leading sign or trailing sign, has an adjusted length less than or equal to 63 decimal digits, whether the operand is a long or short operand, and whether the resulting operand is equal to zero or has an overflow.

Abstract: Information to be written in the form of magnetic flux reversals on the surface of a disk or diskette is applied in serial fashion to a first shift registor. The parallel outputs of the shift register address a PROM. The PROM output is applied to a second shift register in the form of clock and data bits to be written on the disk or diskette magnetic surface. Control signals applied to the PROM address terminals select the mode, FM or MFM, the address mark or if precompensation is required.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle.

Abstract: Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.

Abstract: A cache system includes a high speed storage unit organized into a plurality of levels, each including a number of multiword blocks and at least one multiposition address selection switch and address register. The address switch is connected to receive address signals from a plurality of address sources. The system further includes a directory organized into a plurality of levels for storing address information required for accessing blocks from the cache storage unit and timing circuits for defining first and second halves of a cache cycle of operation. Control circuits coupled to the timing circuits generate control signals for controlling the operation of the address selection switch. During the previous cycle, the control circuits condition the address selector switch to select an address which is loaded into the address register during the previous half cycle. This enables either the accessing of instructions from cache or the writing of data into cache during the first half of the next cache cycle.

Abstract: This relates to an apparatus for performing single error correction, double error detection of binary words, each section of the apparatus processing one byte of raw data. Each section includes first logic means for producing a first plurality of intermediate sector matrix parity outputs. A second logic means receives one of the first plurality of intermediate sector matrix parity outputs and a second plurality of intermediates matrix parity outputs from other sections and generates therefrom a syndrome signal. A third logic means receives this syndrome signal and syndrome signals from other sections and generates therefrom the corrected data bits.

Abstract: A clock system for providing rectangular wave forms or wave trains, with each wave train having a selectable predetermined clock cycle period. A rectangular wave train is generated by a generator comprising a delay line coupled to an INVERTER. By using a second delay line to delay the rectangular wave by a selectable predetermined delay period, a control signal is formed which when fed into the generator produces a second rectangular wave train with a clock cycle period equal to that of the rectangular wave clock cycle period plus the period of the second predetermined delay. The addition of a synchronization circuit permits the clock cycle period to be dynamically selected during a clock cycle. This provides a rectangular train with the period of each clock cycle being any of the predetermined clock cycle periods independent of the clock cycle period of preceding or succeeding clock cycles.

Abstract: A cathode ray tube display terminal system includes a central processor subsystem and a number of certain peripheral subsystems all of which are coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request signals from certain of the peripheral subsystems and on a predetermined priority basis modifies an address generated by the central processor subsystem in dependence upon which of the requesting certain peripheral subsystems has the highest priority. The modified address, called a vectored address points to a firmware subroutine stored in a memory subsystem which is also coupled to the system bus and which processes the interrupt from the highest priority cetain peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single interrupt signal which is also applied to the apparatus in the central processor system.

Abstract: In a microprogrammed data processing system, the throughput of the system is increased during the processing of decimal numeric instructions by apparatus which receives a long operand, greater than a predetermined number of words, which is the result of the calculation, assembles the resultant operand in accordance with an instruction descriptor, and transfers the resultant operand to memory.

Abstract: A logic control system is disclosed for verifying the operability of memory and non-memory data and control paths in both local and remote intersystem link (ISL) units electrically interconnecting a local and remote communication bus in a data processing system. The data processing system may include two or more communication busses each pair of which are electrically interconnected by twin ISL units. The control logic architecture accommodates the receipt of a test mode command from a CPU on a local bus to initiate a test mode operation wherein the memory and non-memory data and control paths of both the local and the remote ISL units are excerised while on-line, and binary coded information received from the local bus is passed through the ISL units, onto the remote bus, and returned to a local bus memory resource for verification. No remote bus resources are used or affected, and the remote ISL unit shall ignore any communications received from any other data processing unit on the remote bus.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.

Abstract: A control store coupled with a central processing unit to transfer information over a common electrical bus and coupled to transfer information over a private interface between the control store and unit. The control store includes firmware words for providing additional control of the unit, which also has a control memory for controlling the operation of the unit. The private interface is used to transfer addressed firmware words from the control store to the unit for use by the unit including generating the next address to be used by the control store, which next address is also provided from the unit to the control store over the private interface. Such private interface is also used to transfer the results of one or more tests performed by the unit, which results indicate which of at least two alternative addresses are to be used by the control store.

Abstract: A logic system in an intersystem link (ISL) unit accommodating the transfer of binary coded information between communication busses in a data processing system is disclosed, wherein dedicated locations in a file register are selected at the bus rate in response to binary coded information received from a local communication bus. ISL transactions to be initiated in response to bus cycle requests thereby are identified. ISL transactions are handled in parallel, and memory transfers are segregated from non-memory transfers to avoid unnecessary delays in memory transfers.

Abstract: A logic system referred to as an intersystem link unit (ISL) is provided for accommodating the transfer of binary coded information between two or more communication busses in a data processing system, wherein information including memory and non-memory read and write requests, CPU to CPU interrupts, peripheral control units to CPU interrupts may be transferred between plural communication busses each supporting plural data processing units including plural CPUs without substantially affecting the bus rate of the individual communication busses. Binary coded information from a communication bus is acquired asynchronously, and plural bus communications of different types are accommodated in parallel. The ISL units further may be dynamically reconfigured to provide for a reallocation of communication bus resources between communication busses.

Abstract: A banking system is provided which is comprised of a central computer, a customer accounts main memory, and plural remote transaction terminals in communication with the central computer. Each remote terminal includes a cash dispensing apparatus, a personal identification number (PIN) signal generator, a random number (RN) signal generator, a security device and a cash dispenser. The communication paths from the RN and PIN signal generators to the security device are wholly contained within the remote terminal and inaccessible to would-be thieves. The remote terminals also include data entry devices activated by a customer to provide a PIN number, a PIN OFFSET number bearing a predetermined relationship to both the PIN number and a customer information file (CIF) signal stored in main memory, and other banking information. In response to a customer-initiated operation, a remote terminal supplies bank transaction and customer identification information to the central computer.

Abstract: A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses.The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

Abstract: A data processing unit's request to a data processing device for the transfer of control and processing of an operation in response to an instruction from the unit, is stalled by the device, dependent on the type of instruction, for a period of time, also dependent on the type of instruction, until the device is ready to process such operation. A shift register arrangement is used in the device, which, dependent on the indicia stored therein, which indicia are appropriately loaded in such register dependent on the type of instruction, is used to delay a response to the unit by requesting the unit to make another request to the device to process the operation called for by the instruction.

Abstract: A cache unit couples between a main store and data processing unit. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes a write command buffer, a transit block buffer and command queue apparatus coupled to the buffers for controlling the sequencing of commands stored in the buffers. The command queue apparatus includes a plurality of multibit storage locations for storing address and control information. The control information is coded to specify the type of command and the number of words the command contains. The address information is used as a pointer for read out of the command from either the write buffer or transit block buffer simplifying control.

Abstract: A microprocessor controlled cathode ray tube display system has a plurality of peripheral devices all connected in common to a system bus. Apparatus in each peripheral device activates a single interrupt signal. A single acknowledge response signal to all the devices enables the interrupting device to place its address signals on the system bus thereby initiating a firmware routine for making the interrupting device operative with the system.