Abstract: A memory subsystem for processing memory requests includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes arrays of memory elements corresponding to a number of storage locations, separate addressing and data output circuits. The system further includes common timing, refresh and control circuits. When the memory request specifies a predetermined type of memory operation, the control circuits generate signals for refreshing a location within the memory unit from which data is not being fetched. The control circuits, upon the completion of the refresh operation, in response to another predetermined memory request, refreshes the corresponding row within the other unit in parallel with fetching data from first unit.

Abstract: Apparatus for cutting segments from a strip of film and for mounting the segments in reusable fixtures. Each segment is severed from the strip and mounted in a single cycle of operation of the apparatus. A cutting die is provided with a nonlinear symmetrical cutting edge lying in a die cutting plane. A punch is provided with a bottom surface substantially the size of a segment. The cutting plane of the punch has a linear punch cutting edge formed at the intersection of the bottom surface and the punch cutting plane, and the punch is mounted in cutting relationship with the die. Positioning means position the strip so that a boundary between segments lies in the die cutting plane. As the punch moves toward the die and a fixture located below the die, a segment is severed from the strip by the cutting action of the punch and die cutting edges which co-operate to minimize the forces applied to the segment tending to change the orientation of the segment to the punch.

Abstract: In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred during asynchronously generated information transfer cycles. Logic is provided for enabling a first unit to transfer first information to a second unit during a first request transfer cycle requesting that the second unit transfer second information to the first unit during a later first response transfer cycle. Logic is also provided to enable the first unit to transfer third information to a third unit during a second request transfer cycle requesting that the third unit transfer fourth information to the first unit during a later second response transfer cycle. Logic is provided that enable the first unit to transfer the third information before receiving the second information and logic is further provided that enables the first unit to receive the second information before or after receiving the fourth information.

Abstract: A cache oriented pipeline data processing unit includes an execution unit, apparatus for fetching data and instructions, hardware decoder and sequencing circuits and a microprogrammed control unit. The microprogrammed control unit includes first and second control stores. The first control store includes a plurality of storage locations, each location for storing at least an address field and a control sequence field for each of the program instructions required to be executed by the data processing unit. The control sequence field is coded to designate which one of a group of hardware control sequences is to be executed by the hardware sequencing circuits for matching the performance of the execution unit and fetching apparatus. The second control store includes a plurality of groups of storage locations, each group for storing the microinstructions required for executing at least a portion of a program instruction.

Abstract: A method of protecting from physical damage the upper surface of medium and large scale integrated IC circuit chips. Certain types of IC chips are provided with a plurality of input/output terminals, or bumps, which project above the upper surface of the chips on which they are formed. The upper surface of each such chip, including its bumps, are spin coated with a thin adhesion promoter which is then dried. The chips and its terminals are next spin coated with a layer of a heat curable resin which is partially cured. The resin and the adhesion promoter are then removed from the upper surfaces of the bump by rubbing with a soft abrasive material. The resin remaining on each IC chip is then finally cured.

Abstract: A logic system is provided for precompensating data and clock bits of a formatted binary information stream during a modified frequency modulation (MFM) encoding for recording on a magnetic medium. The binary information stream is formatted into a gap field, an address preamble field, an address mark field and a data field. Clock bit generation is inhibited during the gap and address preamble fields. Further, a second of three clock bits occurring during the high order half-byte of the address mark field is suppressed to provide a modified MFM (M.sup.2 FM) field. An address mark is provided thereby for indicating the near proximity of a data field. Beginning with the low order half-byte of the address mark field, both MFM clock precompensation and MFM data precompensation is applied as required. The amount of peak shift occurring in the MFM encoded information stream after precompensation is substantially reduced.

Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. Included are a main memory system and a high speed buffer or cache store. System units communicate with each other over the system bus. Apparatus in the cache store monitors each communication between system units to determine if it is a communication from a system unit to main memory which will update a word location in main memory. If that word location is also stored in cache then the word location in cache will be updated in addition to the word location in main memory.

Abstract: A scientific processing unit includes a microprogrammable arithmetic processing apparatus for performing floating point arithmetic operations with operands in long and short form. The apparatus includes a microprogrammable control section and a plurality of microprocessor arithmetic and logic unit chip stages organized into two sections and carry look-ahead circuits coupled thereto. One section includes a predetermined number of series-coupled stages connected to process exponent values or long mantissa values. The other section includes another predetermined number of series coupled stages connected to process short mantissa values. Control circuits interconnect the stages of both sections and connect to the carry look-ahead circuits and to the microprogrammed control section.

Abstract: In a data processing system wherein a plurality of functional units are interconnected by way of a common communication bus in an environment of high data transfer rates, a logic control system is provided for interjecting firmware control during a data transfer between a disk device and main memory to accommodate unsolicited bus requests without incurring data errors or compromising the data transfer rate. Data transferred between the disk device and a disk controller interfacing directly with the common bus is routed through a FIFO (first-in-first-out) buffer under hardware control. The buffer signals the absence of data in its input register and the presence of data in its output register. The signals are logically combined and ANDed with a firmware controlled logic gate to indicate the occurrence of data transfer states. During such transfer states, data is transferred under hardware control between the FIFO buffer and main memory.

Abstract: A method and apparatus for printing electrographically upon two sides of a chemically pre-treated recording medium, at comparatively high speed such as is required in a computer print-out apparatus.A pre-treated paper medium comprised of a conductively treated paper base supporting a plastic dielectric coating on each of its sides, is positioned between electrode assemblies comprised of matrices of a plurality of styli which receive variable information from a data processor, or other equipment and by selectively changing the plurality of styli generating a latent image of alphanumeric characters or other variable printing by electrostatic discharge on the paper which is retained by the coating. The latent image is developed, i.e., made visible, by subjecting the paper medium to charged toning particles suspended in a liquid toning carrier. The image is then fixed, i.e., made permanent by vaporizing the liquid carrier with heat.

Abstract: A data processing system having a system bus; a plurality of system units including a main memory, a cache memory, a central processing unit (CPU) and a communications controller all connected in parallel to the system bus. The controller operates to supervise interconnection between the units via the system bus to transfer data therebetween, and the CPU includes a memory request device for generating data requests in response to the CPU.

Abstract: A microprogrammed pipeline data processing unit includes a first control store, a second control store and a plurality of hardware sequence control circuits. The first control store includes a plurality of storage locations, each location for storing an address field and a control sequence field for each program instruction required to be executed by the processing unit. The second control store includes a plurality of groups of storage locations, each group storing microinstructions required for executing at least a portion of at least one program instruction. Each sequence includes at least one microinstruction which contains a restart field coded to specify the conditions under which the hardware sequence circuits continue instruction execution. For each program instruction which can not be executed by the plurality of hardware sequence circuits in a pipeline mode, the control sequence field is coded to include a predetermined bit pattern.

Abstract: A firmware/hardware method and system is provided for testing interface logic in a data processing system having a plurality of system units intercommunicating over a common electrical bus. Under firmware control, an incorrect parity is generated in a main memory address to be loaded into output registers of a system unit supplying information to the bus. A bus cycle request is issued by the system unit, and when the bus is made available the system unit acknowledges the memory address to initiate a transfer of data from the bus into the input registers of the system unit. Thereafter, the data in the output registers of the device may be compared with the data in the input registers to detect interface logic errors.

Abstract: A logic data control system including a first-in-first-out (FIFO) buffer predictor is provided for the transfer of data between a main memory unit and a peripheral control unit of a data processing system. Data from main memory is stored into the input registers of the peripheral unit, and thereafter loaded into an array of data FIFOs for transfer to a peripheral storage device. A predictor FIFO operates in parallel with the data FIFOs, and is loaded with a dummy or flag byte each time a data request is made to main memory. When a data word is loaded into the data FIFOs, the input register of the predictor FIFO is sensed. If the flag byte in the predictor FIFO has dropped from the input register into the FIFO stack, a request is issued to main memory for an additional data word. When the data FIFOs are filled, the predictor FIFO also is filled and cannot generate an additional data request until a data byte has been unloaded from the data FIFOs to a peripheral storage device.

Abstract: A data processing system includes a plurality of system units all connected in common to a system bus. The system units include a central processor (CPU), a memory system and a high speed buffer or cache system. The cache system is word oriented and comprises a directory, a data buffer and associated control logic. The CPU requests data words by sending a main memory address of the requested data word to the cache system. If the cache does not have the information, apparatus in the cache requests the information from main memory, and in addition, the apparatus requests additional information from consecutively higher addresses. If main memory is busy, the cache has apparatus to request fewer words.

Abstract: A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a store having a plurality of word locations arranged into a number of groups or sets of blocks of word locations, a data directory for storing addresses within a plurality of locations corresponding in number to the number of groups and a control directory including a plurality of multibit locations corresponding in number to the number of groups of blocks. The cache unit further includes an input command buffer for storing commands received by the data processing unit and control logic circuits. The control logic circuits include decoder circuits operative to set to a predetermined state the contents of a predetermined bit of the control directory multibit locations identified by the memory command when the data directory indicates that the information does not reside in the cache unit store.

Abstract: A microprogrammable control unit of a data processing unit includes first and second control stores. The first control store which is addressed initially by the operation code of a program instruction is used for storing a predetermined constant field coded to further specify the operation specified by the instruction operation code in addition to a control sequence field and address field. The second store stores a plurality of microinstructions sequences for executing the repertoire of program instructions. Control unit hardware decoder and sequencing circuits are conditioned by the control sequence field to execute a portion of the program instruction at the completion of which control is transferred to the second control store for completing execution of the program instruction under microprogram control.

Abstract: A microprogrammable control unit of a data processing unit includes first and second control stores. The first control store is addressed initially by the operation code of a program instruction for read out of an address field, a control sequence field and a register control field. The second control store is arranged to store a plurality of microinstruction sequences for executing program instructions. The control sequence field conditions hardware sequence control circuits to execute operations during instruction and cache cycles of program instruction processing. The address field is used for accessing a microinstruction sequence during the execution cycles of program instruction processing for completion of the operation specified by a program instruction.

Abstract: An apparatus for detecting each short circuited diode in a plurality of diodes, coupled in a parallel combination, is disclosed. The apparatus utilizes a flashing light emitting diode to indicate whether the particular diode under test is shorted or not. By utilizing the series inductance associated with each diode circuit, effective isolation of the particular diode under test is obtained for a short duration test pulse and allows the appropriate test to be made.

Abstract: This relates to an apparatus for assigning priority to information temporarily stored in memory controller stack. Associated with each level of the stack is a counter which measures the length of time the information has been stored. A plurality of comparators and associated control logic determines the stack level which contains information which has been stored the longest. If the destination memory associated with the contents of this level becomes available, this level is given priority with respect to transmission to its destination memory.