Abstract: A data processing system includes as part of its power circuits, a number of converter circuits, each coupled to a different one of the power supply units which are to provide different voltages for distribution and use throughout the system. Each of the power supply circuits furnish a 24 volt dc power confidence signal to a central ac power input entry panel which applies the power confidence signals to the converter circuits. Each converter circuit includes an optically coupled isolator circuit which converts the 24 volt dc signal to a noise free low voltage logic level suitable for utilization by the low level high speed logic circuits included within the system. The output noise free low voltages provided by the converter circuits are in turn applied to a corresponding number of confidence input lines of a system interface unit which includes a plurality of ports, each port connected to a different module within the data processing system.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 5-bit bytes and generates a 5-bit binary output byte in accordance with the particular operational mode prescribed by a mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 5-bit input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F= is provided for zero detection purposes. In addition to the arithmetic or logic operations, the unit generates a parity of the half-sums signal HS, a parity of the half-parities signal HP, a parity of the carries signal PC, and a carry error signal CE. A carry-out signal COUT is also generated.

Abstract: An input/output system includes a local memory module including a cache store and a backing store. The system includes a plurality of command modules and a system interface unit having a plurality of ports, each connected to a different one of the command modules and to the local memory module. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. The local memory module includes apparatus operative in response to each memory command to enable the command module to write into cache store the data which is requested to be written into backing store when it is established that such data has been previously stored in cache store.

Abstract: A system and method for providing a control store arrangement in which a single memory having a plurality of memory locations can be used for storing sequences of microinstructions or scratch pad information. The number of storage locations defining the scratch pad area can be increased or decreased as required by assigning tag addresses to a desired number of scratch pad storage locations when the microinstruction routines are being assembled. In this manner, the locations defining the scratch pad areas can be tailored to the particular system operation to be performed. This eliminates the need for modifying the control store circuits to change the size of the control store scratch pad area.

Abstract: A processing unit includes emulation apparatus which operates to execute instructions of a target system, one of a plurality of ways depending upon the options and features of the target system being emulated. The options, features and characteristics of the target system for which the program was originated is defined by the different bits of an option mask word stored within the emulation apparatus. Initially, upon switching to an emulation mode of operation, the emulation apparatus under microprogram control is operative to store signal representations of the option mask word in one of its storage registers. The signals from the stored option mask word are applied to different portions of the emulation apparatus for conditioning the apparatus to execute target system program instructions in accordance with the structural characteristics of the target system for which the program was originated.

Abstract: A system and method for computer process dispatching in a multiprogramming/multiprocessing environment is disclosed. Each process in the multiprogramming/multiprocessing computer system may be in one of four states at any given time as follows:1. Running -- the process is in control of the computer system and is directing the operation of the central processing unit (CPU);2. ready -- the process is ready to run as soon as it is given control of the CPU;3. waiting -- the process is waiting for an external event to occur so it can either resume running or enter the ready state;4. Suspended -- the process has been temporarily stopped (from a source external to the process).The dispatcher is a firmware/hardware structure that controls the first three states of the process--i.e. running, ready and waiting states.

Abstract: A system and method for computer process control in a multiprogramming/multiprocessing environment is disclosed. Each process in the system is associated with a process control block (PCB) hardware structure which is identified by its logical address (J,P). The PCB acts as a virtual processor with null speed when, in fact, no real processor is assigned to the process. As utilized in a multiprogramming environment a virtual process (PCB) is substituted for the real processor (i.e. central processing unit, CPU) whenever the only job of the processor is to listen for a signal to be sent by another processor and to restitute the real processor to the process when, or after, the signal has arrived. The circumstances where a process starts using a processor solely as an "ear" are as follows:A. when the process state switches from a running state to a waiting state; orB. when the process state switches from a running state to a suspended state.In both instances the CPU is given away and replaced by the PCB.

Abstract: A current mode arithmetic logic circuit utilizes a unique combination of a 4-bit and a 5-bit arithmetic logic unit for performing parity prediction and parity checking on an n-bit byte plus parity, in addition to performing 16 binary or 16 Boolean operations on two n-bit plus parity bytes.

Abstract: A memory system includes a cache store and a backing store. The cache store provides fast access to blocks of information previously fetched from the backing store in response to commands. The backing store includes error detection and correction apparatus for detecting and correcting errors in the information read from backing store during a backing store cycle of operation. The cache store includes parity generation circuits which generate check bits for the addresses to be written into a directory associated therewith. Additionally, the cache store includes parity check circuits for detecting errors in the addresses and information read from the cache store during a read cycle of operation. The memory system further includes control apparatus for enabling for operation, the backing store and cache store in response to the commands. The control apparatus includes circuits which couples to the parity check circuits.

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes.

Abstract: An input/output system couples to a host processor through a system interface unit and includes at least two input/output processing units and a memory unit. The system interface unit includes interrupt processing logic circuits for each input/output processing unit for processing interrupt requests on a priority basis. The system interface unit further includes a processor intercommunication network which connects to each of the interrupt processing logic circuits.The input/output operating system initiates an input/output operation in response to a connect interrupt generated by the host processor executing a connect instruction. The interrupt is directed to an assigned input/output processing unit by the System Interface Unit (SIU). The assigned processor executes an instruction sequence which causes an appropriate entry to be placed in an operating system queue located within the memory unit. The queue entry has sufficient data to specify the desired I/O operation.

Abstract: A machine for blanking an integrated circuit chip from a segment of a film strip held in a fixture, forming its leads, and placing the chip on a multilayer substrate. The fixtures are stacked in a magazine which is mounted on the machine. A transfer mechanism transfers one fixture at a time from the magazine to a punch press where the IC chip is blanked from its film segment, and its leads are formed. The punch is retracted, and a multilayer substrate, which is mounted on an X-Y table, is positioned by the table under the punch so that the excised chip is directly above a chip pad and the chip leads are above the chip lead pads of a predetermined chip pad. The punch is lowered to position the chip on its chip pad. The substrate is coated with an adhesive flux to retain the chips and their leads in place. The punch is retracted and the X-Y table is moved to clear the punch press. A microcomputer controls the machine.

Abstract: An improved binary/binary coded decimal arithmetic logic unit employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal (BCD) data. The unit performs 16 binary and 2 decimal arithmetic operations and 16 Boolean operations on two 4-bit plus parity input fields. The particular operation is determined by a 5-bit mode control signal. A carry-in input CIN, duplicate carry-in input CIND, parity check PCK input, invert parity input IP, decimal mode signal D, and decimal add input DA are also provided. The device generates a binary output resultant of the operation defined by the mode control signal. In addition to the arithmetic or logic operations, the unit performs parity checking, parity carry, and parity prediction operations on 4-bit plus parity binary and BCD fields.

Abstract: In a large scale data processing system employing partitioning, paging and segmentation techniques with a descriptor enforced access to storage areas, a method and apparatus for testing address formulation is disclosed. All fundamental steps in address preparation are preserved whether a single step formulation is possible, as when the page table words are present in associative memory, or a multiple step process is required, as when the page table words must be retrieved from main memory.

Abstract: A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.

Abstract: A main memory system includes encoder and decoder circuits. The encoder circuits are connected to receive data bits and parity bits and from them generate check code bits which are stored with the data bits during a write cycle of operation. The decoder circuits are connected to receive data and check bits read out from memory during a read cycle of operation. The decoder circuits include a plurality of decoder circuits and error locator circuits. Circuits via exclusive OR circuits generate a number of syndrome bit signals. These signals are divided into first and second groups. The first group is coded to specify which one of a number of decoder circuits comprising the error locator circuits is to be enabled in the case of an error condition. The second group of signals is coded to designate the particular data bit to be corrected by the decoder circuits.

Abstract: A multiprogrammable/multiprocessing digital computer system having a process control block for each process in the system, wherein each process control block includes information which specifies the state of a processor at any given time. Associated with each process control block is a decor extension table having information to indicate whether a specified function, such as the emulation of another processor, may be executed in the system. A native mode instruction indicating a specified function for either one instruction or for a plurality of instructions, is first checked to determine proper format, after which a determination is made by means of the decor extension table, as to whether or not the system is capable of executing the specified function indicated by the native mode instruction.

Abstract: A local memory of an input/output system includes a cache store and a backing store. The system includes a plurality of command modules. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. Each memory command applied to the memory unit incudes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store. The local memory unit includes aparatus operative in response to each memory command to enable the command module to bypass selectively the cache store in accordance with the coding of the predetermined bit thereby enabling the command modules to execute operations more expeditiously during the performance of input/output data transfer operations.

Abstract: A plurality of trap save areas are linked to form a pool of such areas from which an area may be loaded with context from various sources in response to a trap condition, such as the addressing of unuseable memory, the loaded area unlinked from the pool, and various pointers changed to reflect such unlinking. The unlinked area is associated with the process which was executing at the time of the occurrence of the trap condition by effectively being coupled to the interrupt level of such process. Independent of the interrupt level, a trap handler routine, specific to the nature of the trap condition, is executed following which the unlinked area is returned to the pool and the various pointers changed to reflect such return.

Abstract: Apparatus and method are included in the main memory of the data processing system which receives data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies a plurality of data byte signals together with associated parity bits for writing into an addressed storage location of memory. Error detection and correction encoder circuits are connected to receive the data bits and parity bits and from them generate check code bits which are coded to signal selectively the presence of an uncorrectable error condition in accordance with the parity bits from a given source.