Abstract: A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus, eliminating at least one step in returning to a common address for starting the execution of another microprogram.

Abstract: A system clock mechanism which can be either stalled (i.e. held indefinitely in a high state) or stretched (i.e. change the rate of pulse occurrence). A first electronic circuit provides pulses having a first predetermined pulse period T.sub.1 with each pulse being generated at a first predetermined rate. A second electronic circuit cooperating with the first electronic circuit modifies the first electronic pulses to generate pulses at a second predetermined rate having a second predetermined pulse period T.sub.2. A third electronic circuit cooperating with the first and second electronic circuits holds the clock circuit indefinitely in a high state.

Abstract: Apparatus for blanking an integrated circuit (I.C.) chip and the chip's thin flexible ductile leads which extend beyond the four sides of each chip from a segment of film to which the leads are attached and forming the leads including forming a foot at the free end of each lead of the chip in a single operation of a hollow punch having contiguous cutting and forming edges with a contiguous forming surface between them and a hollow die having cutting edges with a forming block having contiguous forming edges and forming shoulders positioned within the die. The punch and die are mounted on a punch press. Alignment means accurately position the chip and its leads with respect to the punch and die. A pressure pad is mounted in the punch and presses the leads against a portion of the forming block to isolate the bonds between the leads and the integrated circuit chip from forces applied to the leads during cutting and forming.

Abstract: Data stored in a selected block of a memory associated with a data processing system is protected while a first device has access to any memory location in the selected memory block. If another device seeks access to the selected block of memory for the purpose of performing one or more predetermined unique sequences of operation while the first device is carrying any of such operations with respect to the selected memory block, the other device is locked out by means of a signal instructing it to abort the operation for which access is sought. Upon completion of the operation sequence by the first device, the selected memory block is unlocked and access is again available to any device. Further, a device addressing a location of memory for the purpose of carrying out one of a plurality of predetermined unique sequences is informed of the occurrence of events of significance to it by forcing an address register to a predetermined memory location comprised of a plurality of interrupt cells.

Abstract: Interrupt service is enabled for either a real-time clock or watchdog timer time out condition. A mode register is provided to effectively enable or disable the interrupt apparatus and if enabled is coupled to enable a service register in response to repetitively occurring clock pulses. Each time the service register is enabled, a counter is changed in value until a predetermined value is indicated at which time interrupt service is enabled at an interrupt level specified by the operator. Further, facilities are provided for presetting the value of the counter in an expeditious manner.

Abstract: An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit.

Abstract: A common electrical bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchronous manner. Each of the units includes priority logic which includes logic elements for requesting a bus cycle, such request being granted if no other higher priority unit has also requested a bus cycle. The request for and an indication of the grant of the bus cycle are stored in each unit so requesting and being granted the bus cycle respectively, only one such unit being capable of having the grant of a bus cycle at any given time, whereas any number of such units may have its request pending at any particular time.

Abstract: A general mechanism and a family of hardware/firmware instructions are disclosed, which allow sharing files and resources without interference one from the other in a multiprogramming, multiprocessing environment. The basic inventive concept of interference is developed and several embodiments of the invention are disclosed. Protective mechanisms determine when sharing of files or resources is safe, and provide alternate courses of action to be taken by the computer system when it is determined that sharing would provide wrong results.

Abstract: Method and apparatus are disclosed for the serial transfer of data in a clockless manner. Data is transmitted in the form of signal state changes from a dispatcher to a receptor. The receptor is operative to translate the signal state changes into data and thereafter signal the data dispatcher that it has done so. The dispatcher is operative to transmit the next piece of data only after it has been appropriately signalled by the receptor.In accordance with another aspect of the invention, the dispatcher is capable of notifying the receptor when an end to the transmittal of data has occurred. The data receptor does not signal the dispatcher for further data when this occurs. The receptor instead signals a data sink that the previously transmitted data is available for copying. The data sink copies the data and thereafter authorizes the receptor to initiate further data receiving operations.

Abstract: A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the rectified AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transformers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner. An overcurrent sensing and control device prevents damage to components. The power on/fail circuit signals the load as to the status of the regulated load voltage and guarantees power for orderly shutdown after an input power outage.

Abstract: A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the rectified AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transformers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner. An overcurrent sensing and control device prevents damage to components.

Abstract: A 5-bit D-type master/slave counter/shift register with buffered outputs is disclosed. The counter implements the load, count up, count down, and reset functions and also has the capability to be reconfigured into an inverting serial shift register for Non-Functional Test (NFT) techniques. In addition, the fifth bit may optionally be removed from the counter logic and used as a parity bit, although it will be necessary to use some external logic to implement this parity function.

Abstract: In a data processing system employing paging and segmentation for storing information in memory, the input-output unit is provided with addressing capability for addressing and accessing memory without the intervention of the central processing unit. Page tables are set up in memory containing page table words, and a page table is assigned to each peripheral. A peripheral control word assigned to each peripheral includes a pointer to the start of the peripheral's page table whereby the peripheral through the I/O unit can locate its assigned page table, and page table words therein are combined with other control words to access paged memory locations.In one mode of operation an extended addressing mechanism is provided which allows the generation of absolute addresses of paged memory locations having an address field larger than the address field of the control words used to access such paged memory locations.

Abstract: Today's cathode ray tube oscilloscopes are widely used throughout the world and form an important basic tool in many industries. An apparatus to modulate the cathode ray display intensity, thereby enhancing the oscilloscope's capabilities in that it can now make more accurate measurements and, in effect, increase its band width, is disclosed. The apparatus to facilitate this effect is light weight, low cost, and easily connected to almost all oscilloscopes now in use.

Abstract: An input/output processing system comprises a number of modules including at least a pair of processing units connected to operate as a logical pair and a system interface unit having a number of ports. Each port connects to a different one of the modules for interconnecting pairs of modules for communication over a number of switching circuit networks included in the system interface unit. The system interface unit further includes control logic circuits for disconnecting each processor of the logical pair preventing the disconnected processing unit from communicating with other modules. The control logic circuits further include circuits which in response to special commands from a good processor are operative to condition via a special line, circuits in the disconnected processing unit to apply status signals representative of the contents of a control register to the system interface unit.

Abstract: A charge-coupled device (CCD) for amplifying and accumulating charge comprises a first CCD line, a plurality of time-independent CCD charge amplifiers each having an input gate connected to a surface potential tap on a respective one of the charge storage regions of the first CCD line, and a second CCD line for accumulating the charge which has been amplified by the charge amplifiers. The device permits the coherent accumulation of the charge in a time-independent manner. Arithmetic, logic, and complex signal processing functions may be conducted by suitable configurations of the charge amplifiers.

Abstract: A program switching monitor is provided with means for preventing a central processing unit operating under control of a first program from switching to another program until certain conditions are met. Upon receipt of indications or data representative of the fact that all commands issued while the unit was operating under the control of the first program have been accounted for, program switching is permitted.

Abstract: An input/output system includes a plurality of modules and a system interface unit having a plurality of ports, each of which connects to a different one of the modules. The plurality of modules includes at least one processor and one memory module. The system interface unit includes a timer unit and a priority network for processing processor interrupt requests on a priority basis. The priority network connects to a register for storing coded priority level signals to be assigned to the different types of interrupt requests. The register is conditioned to store a low priority level for timer interrupts. The timer unit includes a preset register, an interval counter and a rollover counter. At the completion of each time interval, the interval counter is loaded automatically from the preset register and counting is continued. Simultaneously, the interval counter conditions the rollover counter to store a count registering the total number of completed intervals counted.

Abstract: A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system by eliminating a ROM address register for addressing microwords. The method or apparatus incorporates the use of a predetermined bit position in the microinstruction word which is set to a binary one when the microword is the last microword of an executing microprogram. The apparatus is responsive to the electronic representation of the binary one signal to cause the microinstruction execution sequence to branch to a predetermined location in the microprogram memory for execution of the following microinstruction; thus eliminating one ROM address register and at least one step in returning to a common address for starting the execution of another microprogram.

Abstract: Two numbers are multiplied together without first changing either of them, if negative, to a positive number, thereby minimizing the time required in the multiplication process. In the multiplication, depending upon the sign of the multiplier and the sign of a bit in a predetermined bit location of the multiplier as shifted in a shift register, the multiplier and the multiplicand are operated on by either a shift operation or operated on by a shift and add operation.