Abstract: A control store having a first portion for storing system operation instructions (opcodes), a second portion for storing control store addressing information, wherein the second portion includes a greater number of storage locations than does the first portion in order to efficiently store different control store address information which may be required for the same opcode. Addressing apparatus coupled to address a location in the first portion and any one of at least two corresponding locations in the second portion is provided, thereby minimizing the number of locations required in the first portion of the control store.

Abstract: A current mode 20-bit memory is organized as four words each containing five bits. The memory comprises a clock circuit a data-in circuit, comprising a plurality of data selectors and master latch registers, a data-out circuit comprising two independent sets of output buffers, two independent read select circuits, a write select circuit, a 4x5 matrix of memory cells, and non-functional testing circuit. In one mode data may be independently read from any two words at the same time that data is written into any one word. In another mode, all bits in a selected word may be synchronously reset. In a third mode the storage elements associated with one selected word may be configured as an inverting shift register for testing and diagnostic purposes. The device is implemented in current mode logic, and a portion of the circuitry operates on differential level signals for increased operational speed and efficiency.

Abstract: An automatic reconfiguration hardware capability for automatically altering the local memory/processor configuration and reinitiating a bootload sequence in the event of a failure in the start-up phase of the input/output processor bootload. The automatic reconfiguration logic is enabled when a bootload request originates from the system console or the central system. Once a bootload request is initiated, all possible local memory/input-output processor (IOPP) configurations are attempted without further manual intervention. If no configuration is successful, a bootload error indication is presented at the I0P configuration panel.

Abstract: A reusable fixture for a segment of a film strip having a flexible beam lead frame mounted on the segment and an integrated circuit chip bonded to the inner portions of the leads of the lead frame. The fixture is made from an integral laminar layer of a suitable material. The improvements are in providing a plurality of pairs of projections with protuberances which overlie, to a slight degree, the attachment webs of a segment. The fixture is also provided with detachment openings to provide access to the attachment webs which detachment openings facilitate removal of a segment from the fixture.

Abstract: A data field descriptor extends the flexibility of operand accesses by defining the attributes of a data field with regard to length, location and form of data representation at execution time. This delay of binding the operand accesses until execution time supports both data independence and security by permitting programs to be compiled without any restrictions imposed by the attributes of data fields. At execution time the necessary information is provided through a register so that the data field information may be correctly processed. With this feature a program is permitted to survive the change in formats of its input and output files without repeatedly undergoing the expensive operation of compilation. Also permitted is processing of files containing data field values which are not uniformly formatted throughout the file but which are self-defining through a data field descriptor.

Abstract: An apparatus for utilizing a logical compare instruction is disclosed. The apparatus develops a data field descriptor associated with and describing the attributes of each of the operands of the compare instruction. If the operands have different formats, when matching the contents of a first operand to the contents of a second operand, one operand is converted at execution time of the compare instruction to a format consistent with the other operand. The apparatus determines whether the contents of the first operand is greater than, less than, or equal to the second operand.

Abstract: Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address signals and does not permit the application of the CAS signal to memory until the worst case delay of the memory address signals has been accounted for.A memory array is comprised of any combination of latched or non-latched tri-state memories. The latched memories are coupled to a data bus utilizing conventional TTL circuits in combination with a power driver to simulate conventional tri-state buffer circuits. When the power driver/drivers remove(s) power from TTL circuits, the tri-state characteristics are simulated; whereas when the power driver applies power to the TTL circuits, they operate in their normal mode and present a normal impedance between the data bus and data-out lines of the memory array.

Abstract: A power supply provides a low-level DC voltage to DC load circuits by first rectifying the standard AC voltage and thereafter reducing the rectified AC voltage to the low-level DC voltage. The reduction of the rectified AC voltage to the low-level DC voltage is accomplished by a power transformer which is switched on or off by a pair of switching transistors. The switching transistors are operated in a "push-pull" mode by a pair of control transformers operating in combination with a control circuit. The control circuit produces various pulse conditions in the control transformers which turn their respective switching transistors on and off in a prescribed manner.

Abstract: A touch sensitive device includes an arrangement of conductors in combination with a pressure sensitive electrically conductive material. The conductors appear in a cross-wire matrix imprinted on the top and bottom surfaces of a rigid printed circuit board. The pressure sensitive electrically conductive material is positioned over the cross-wire matrix of spaced electrical conductors. The resulting arrangement defines a plurality of touch sensitive locations which may be used for uniquely entering information in a data entry system.

Abstract: Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

Abstract: A microprogrammable peripheral controller in addition to being operative to controlling plurality of input/output devices in response to commands for processing information signals from a magnetic medium also includes apparatus for independently establishing a minimum operating capability within the controller. The apparatus includes a read-only control store arranged to store microinstructions and a limited number of basic bit patterns. The apparatus in response to an external control signal is operative to condition the data recovery apparatus included in the controller to receive the blocks of synchronization and data patterns arranged in a predetermined format and generated from basic bit patterns obtained from the control store. Simultaneously therewith, the apparatus inhibits normal transfer of information from the magnetic medium.

Abstract: A circuit for energizing the electromagnet of the print head of a high speed impact printer, wherein such circuit operates effectively with an unregulated supply voltage by providing energization current pulses whose level and duration are dependent on the present level of such supply voltage.

Abstract: A READ ONLY memory is disclosed wherein the bits of a given word are separately stored in a number of individual storage arrays. The individual storage arrays each contain a plurality of addressable bit storage locations. These bit storage locations are first accessed and thereafter sensed in response to a given address. The accessing and sensing is implemented by current mode logic in a manner which effectively develops and thereafter utilizes various current paths.

Abstract: A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.

Abstract: A high density magnetic read head is designed to yield an increased read signal. The width of the read head is reduced by folding a magnetoresistive sensor strip into U-shaped loops. The loops are folded one upon another in a plane perpendicular to the plane of the storage medium. By folding the sensor strip, the shape anisotropy of the sensor is increased and the single domain condition of the sensor in the desired direction is maintained.

Abstract: An improved drive coil for a magnetic domain memory device has varying separation between adjacent conductors to improve the uniformity of the magnetic field.

Abstract: One of a series of hardware/firmware primitives is disclosed for converting a general purpose digital computer into a database machine. The invention comprises a hardware/firmware implemented machine instruction which determines the appropriate register where a database pointer is currently stored, retrieves the pointer from that register and then stores the pointer into main memory.

Abstract: Apparatus and a method for coupling and uncoupling data-read lines of a memory array to a data bus. The data read-out lines of a memory array which is comprised of any combination of latched or non-latched tri-state memories are coupled to the data bus utilizing a conventional TTL circuit in combination with a power driver to simulate a tri-state buffer circuit. When the power driver removes power from the TTL circuit, a tri-state circuit is simulated; whereas when the power driver applies power to the TTL circuit, it operates in its normal mode and a normal impedance is presented between the data bus and the data-out lines of the memory array.

Abstract: The invention disclosed reduces unrecoverable read errors from a magnetic tape resulting from the apparent lack of a cyclic check character (CCC), sometimes referred to as a cyclic redundancy check character, or a longitudinal check character (LCC), sometimes referred to as a longitudinal redundancy check character. The detector provides a variable read window to synchronize receipt of the CCC and/or LCC with their associated data blocks even though the CCC and/or LCC was not written in the appropriate time frame called for by the write specification of the tape in question.