Patents Represented by Attorney, Agent or Law Firm Rosenman & Colin, LLP
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Patent number: 6399990Abstract: The present invention relates generally to protection of integrated circuits from electrostatic discharges and more specifically to the use of devices formed in isolated well regions for electrostatic discharge protection. One aspect of the present invention is an ESD protection circuit that includes a first FET and a second FET. The drain of the first FET is coupled to an ESD susceptible node and the source of the first FET is coupled to a first voltage terminal. The gate and a well of the first FET are coupled together and to the drain of the second FET. The source of the second FET is coupled to the first voltage terminal. The gate of the second FET is coupled to a second voltage terminal. The second voltage terminal is connected to a voltage source that is at the first voltage when the circuit is not powered, and at a voltage above the threshold voltage of the second FET when the circuit is powered. The well in which the first FET is formed is electrically isolated from other wells in the substrate.Type: GrantFiled: March 21, 2000Date of Patent: June 4, 2002Assignee: International Business Machines CorporationInventors: Ciaran J. Brennan, Mark D. Jacunski, Michael A. Killian, William R. Tonti
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Patent number: 6393051Abstract: A digital subscriber line communicating system and a transceiver therein are disclosed. The system or the transceiver comprises: a unit for calculating a bitmap which defines the number of transmissible bits for each carrier signal in each of periodical noise durations and a rate converter for converting a constant rate of an input transmitting data into a rate determined by the bitmap, and for adding, in a predetermined number of the periodical noise durations, dummy bits to the data having the converted rate. The bitmap calculating unit includes: a line quality measuring unit for measuring the quality of the communication line in each of the periodical noise durations, a transmission bit number converter for calculating the number of transmissible bits to be allocated to each carrier to form the bitmap, and a bitmap optimizing unit for minimizing the dummy bits by decreasing the number of the transmissible bits allocated to each carrier signal of the symbols.Type: GrantFiled: June 29, 1999Date of Patent: May 21, 2002Assignee: Fujitsu LimitedInventors: Nobukazu Koizumi, Seiji Miyoshi, Takashi Sasaki, Kazutomo Hasegawa
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Patent number: 6389790Abstract: Several methods of forming links for use with the creation of rope chains is disclosed, whereby the outer peripheries of such links are contoured prior to assembly into rope chains. In one embodiment, the wire used in the formation of intertwinable links is contoured and then cut into individual, pre-contoured links. In another embodiment, the outer periphery of non-contoured links are individually contoured prior to the intertwining of such links to form actual rope chains. In another embodiment, individual links are stamped with inner and outer peripheries of different shapes. In yet another embodiment, individual links are collectively contoured, preferably after arrangement on a support such as an ice lathe or a mandril. Such contouring can be accomplished by hand, machine or the like. If such links are not already provided with a gap, then a gap can be formed into the links as part of the contouring step.Type: GrantFiled: December 29, 1999Date of Patent: May 21, 2002Assignee: D & W Jewelry Inc. (NY Corporation)Inventors: David Rosenwasser, Avraham Moshe Rosenwasser
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Patent number: 6392262Abstract: An indium layer sandwiched between palladium layers are treated with heat so that the indium is diffused into a p-type gallium arsenide, and is alloyed with the palladium, whereby the p-type indium gallium arsenide layer decreases a Schottky barrier between the p-type gallium arsenide and the palladium-indium alloy layer.Type: GrantFiled: January 27, 2000Date of Patent: May 21, 2002Assignee: NEC CorporationInventor: Yasushi Shiraishi
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Patent number: 6389701Abstract: A hand tool is fitted with a fixed shield and a movable shield which is rotatably mounted around the fixed shield. The two shields are aligned with one another by each shield being keyed into a countersunk washer formed with an anchor slot for the fixed shield and a semi-annular guideway for the movable shield. A torsion spring normally biases the movable shield into a closed position about the fixed shield.Type: GrantFiled: December 17, 1999Date of Patent: May 21, 2002Assignee: Gyros Precision Tools, Inc.Inventor: Leonard Friedland
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Patent number: 6390831Abstract: A shelf-type telecommunications device has a back wired board assembly mounted on a back of a shelf unit into which a plurality of plug-in units are inserted side by side. The back wired board assembly has a main back wired board to which at least one plug-in unit is connected and a sub back wired board to which at least one external cable is connected, the outer surface of the main back wired board and the inner surface of the sub back wired board opposing each other. The main back wired board and the sub back wired board are fitted together by using a plurality of relay connectors or pin terminals so as to electrically connect the main back wired board and the sub back wired board to each other without the need for coaxial cables, thus reducing the size of the device.Type: GrantFiled: July 2, 1999Date of Patent: May 21, 2002Assignee: Fujitsu LimitedInventors: Shozo Shimada, Hirofumi Imabayashi, Mitsuo Kaetsu, Noboru Nakama, Takashi Sekiguchi
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Patent number: 6393532Abstract: In data insertion control technique; a plurality of buffers hold different types of data, which are to be inserted into a predetermined transmission medium and are equal in insertion priority, and a data insertion controller controls the data insertion order in which the data are to be inserted into the transmission medium by controlling the read process order in which the different types of data are to read from the buffers, based on the write process order in which the different types of data have been stored in the buffers. The result is that it is possible to realize exact data insertion in a minimum delay time.Type: GrantFiled: June 22, 1999Date of Patent: May 21, 2002Assignee: Fujitsu LimitedInventors: Syuji Takada, Yasuhiro Ooba
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Patent number: 6392491Abstract: The amplification element is configured by amplifying a multicarrier signal by combining plural carrier waves modulated independently There is disclosed a high-frequency amplifier for amplifying multicarrier signals generated by combining plural carrier waves modulated independently. The amplifier performs a predetermined filtering processing at its output end. An amplification element is also disclosed which is integrated with a circuit for suppressing main components of nonlinear distortions, thus forming an integrated circuit. In electronic appliances, equipments, or systems to which the invention is applied, achievement of reduction in price and size, improvement in reliability, and maintenance and operation being done more efficiently at reduced costs can be accomplished.Type: GrantFiled: December 29, 1999Date of Patent: May 21, 2002Assignee: Fujitsu LimitedInventors: Shigeru Ohkawa, Kiyotaka Takahashi, Takumi Takayashiki
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Patent number: 6388530Abstract: A microwave amplifier circuit controls the output power thereof depending upon an associated transmitter of a wireless telephone, and a main amplifier transistor and switching transistors of a drain bias controlling circuit are implemented by gallium-arsenide heterojunction field effect transistors so that, even if they are integrated on a single compound semiconductor substrate, the microwave amplifier circuit achieves a high power efficiency over a wide output voltage range.Type: GrantFiled: December 28, 1999Date of Patent: May 14, 2002Assignee: NEC CorporationInventors: Takeshi Nishimura, Naotaka Iwata
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Patent number: 6387821Abstract: In a method of manufacturing a semiconductor device having a multi-layer interconnection, after a via hole has been formed, the inside of the via hole is cleaned using a cleaning solution containing a complexing agent capable of forming a complex with contaminants of copper type metals.Type: GrantFiled: September 30, 1999Date of Patent: May 14, 2002Assignee: NEC CorporationInventor: Hidemitsu Aoki
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Patent number: 6389288Abstract: A mobile communication terminal includes: a reported location information detecting unit for detecting reported location information from a base station; a reported location information managing unit for managing one of the reported location information specified by a user and a variation of the reported location information specified by the user; a registered process executing unit for executing, when it is determined that the reported location information detected by the reported location information detecting unit matches the reported location information managed by the reported location information managing unit, a predetermined process that corresponds to the reported location information producing the match.Type: GrantFiled: March 27, 1998Date of Patent: May 14, 2002Assignee: Fujitsu LimitedInventors: Soichi Kuwahara, Keiki Nishihara
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Patent number: 6388879Abstract: A circuit board packaging structure comprises a plurality of circuit boards disposed in parallel to each other and each packaged with electric circuit parts. The circuit board packaged with electric circuit parts exhibiting a larger exothermic quantity than those of the electric circuit parts packaged on the other circuit boards is disposed outermost among the plurality of circuit boards. The surface of the circuit board packed with the electric circuit parts exhibiting the larger exothermic quantity is directed outside the structure.Type: GrantFiled: February 9, 1995Date of Patent: May 14, 2002Assignee: Fujitsu LimitedInventors: Hiroyuki Otaguro, Takayuki Ashida, Hitoshi Yokemura, Hidenao Nakajima, Yoshimi Watanabe, Shuuhei Fujita
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Patent number: 6387948Abstract: 8-Acetylarteminolide of the formula (I) having inhibitory activities against farnesyl-protein transferase(FPTase), a progression of the cell cycle and angiogenesis may be useful for the prevention and treatment of various cancers and angiogenesis-related diseases:Type: GrantFiled: June 17, 2000Date of Patent: May 14, 2002Assignee: Korea Research Institute of Bioscience and BiotechnologyInventors: Byoung-Mog Kwon, Kwang-Hee Son, Ha-Won Jeong, Seung-Ho Lee, Mi-Young Han, Hyun-Mi Kang, Hyae-Kyeong Kim, Soo-Ik Chang
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Patent number: 6385741Abstract: A method and an apparatus for selecting test sequences that comprises preparing tree-structured state transition data associated with state transition weights from state transition data, extracting test sequences from the tree-structured state transition data, and repeating processes of determining averaged weight for each of the test sequences, selecting a test sequence by which the average is maximum, and decrementing the weights contained in the selected test sequence by one unit to prioritize the test sequences.Type: GrantFiled: May 26, 1999Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventor: Mitsuhiro Nakamura
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Patent number: 6385754Abstract: A monitor and control system for transmission devices, by which mounting dimensions can be reduced, consumption power can be lowered and the cost can be reduced by reducing a number of connectors connecting units and reducing a number of drivers and receiver ICs is provided. In the monitor and control system for transmission devices, each having a monitor and control package, and plural monitored and controlled packages connected to the monitor and control package through serial buses, the monitor and control package monitors the plural monitored and controlled packages.Type: GrantFiled: December 22, 1998Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventors: Koji Mizumoto, Toshiaki Hayashi, Masataka Yasunaga, Kenichi Kuwano
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Patent number: 6385213Abstract: In processing a frame synchronous pattern, a data switch section arranges in such a manner that an object frame synchronous pattern comes as a start of the parallel data, and a provisional-region detection section for samples, among the parallel data, a part in which the object frame synchronous pattern is presumably located, as a provisional region, and converts the parallel data of the provisional region in serial. And a frame synchronous pattern detecting section detects the object frame synchronous pattern from the partial serial data of the sampling and converted and responsive to the frame synchronous pattern detection section and the provisional-region detection section. A data switch control section, controls the data switch section based on the output of the provisional-region detection section and the output of the frame synchronous pattern detection section.Type: GrantFiled: June 23, 1997Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventors: Yoshinori Nakamura, Kazuo Takatsu
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Patent number: 6385167Abstract: There is provided an ATM switch including: an input line unit for terminating ATM cells input via an input connection; an output line unit for outputting ATM cells to an output connection; and a switch unit for switching a first ATM connection formed by linking a first input connection with a first output connection via a first internal connection, to a second ATM connection, which has the same bandwidth and quality as the first ATM connection, formed by linking a second input connection with a second output connection via the first internal connection. With this arrangement, when the first ATM connection is changed by channel switching to the second ATM connection, the first internal connection at the first ATM connection before the switching is employed for the linking of the second input connection with the second output connection at the second ATM connection.Type: GrantFiled: April 5, 1999Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventor: Toshiyuki Kamo
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Patent number: 6385116Abstract: A semiconductor integrated device includes a functional circuit which has a plurality of signal terminals and an ESD protective circuit for protecting the functional circuit including a pair of protective diodes connected in a reverse direction between each of the signal terminals and a power source line or a ground line. The EDS protective circuit further has a bipolar transistor having a current path between the power source line and the ground line, and a capacitor connected between a collector and a base of the bipolar transistor. The protection against the ESD effectively functions when a surge is applied between the signal terminals because the current path for flowing the discharge current is formed.Type: GrantFiled: March 1, 2001Date of Patent: May 7, 2002Assignee: NEC CorporationInventor: Jianqin Wang
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Patent number: 6385181Abstract: An array antenna system of a wireless base station in CDMA mobile communications has a beam former for forming a plurality of electric beams by applying beam forming to multipath signals received by a plurality of antenna elements of an array antenna and inputting the beams to despreading/delay-adjusting units (fingers) provided for respective path of multipaths. Each finger despreads each of the plurality of beams input thereto. A beam selector selects despread signals for which desired signal components are large from all beams of all paths, a combiner weights and combines the selected despread signals, and an decision unit decides data based upon the combined signal.Type: GrantFiled: August 31, 1998Date of Patent: May 7, 2002Assignee: Fujitsu LimitedInventors: Masafumi Tsutsui, Yoshinori Tanaka, Shuji Kobayakawa
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Patent number: D456624Type: GrantFiled: November 30, 2000Date of Patent: May 7, 2002Assignee: Asientos Esteban, S.L.Inventor: D. Jaime Gil Unamuno