Patents Represented by Attorney, Agent or Law Firm Rosenthal & Osha L.L.P.
  • Patent number: 6446168
    Abstract: A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry for switching between the first mapping scheme and the second mapping scheme. The microprocessor is in communication with the cache through the switching circuitry and stores information within the cache using one of the first mapping scheme and second mapping scheme. Also, monitoring circuitry for determining whether one of instructions and load/store operations is using the cache is included. Further, the switching circuitry switches between the first mapping scheme and the second mapping scheme based on which one of instructions and load/store operations is using the cache.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: September 3, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Kevin Normoyle, Bruce E. Petrick
  • Patent number: 6445197
    Abstract: An electron beam tester, recording medium and a signal data detecting method capable of detecting whether or not the signal at a predetermined position of an electric component contains a jitter.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: September 3, 2002
    Assignee: Advantest Corporation
    Inventor: Masayuki Kuribara
  • Patent number: 6441656
    Abstract: A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Gin S. Yee, Drew G. Doblar
  • Patent number: 6442099
    Abstract: A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when accessing data from a segmented bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells or segments they are in get closer to an output of the segmented bit line structure. Further, a method and apparatus for consuming low power when accessing data from a differential bit line structure in a register file is provided by using transistors having progressively smaller widths as the storage cells they are in get closer to an output of the differential bit line structure.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Shree Kant, Gajendra P. Singh
  • Patent number: 6439062
    Abstract: An apparatus for detecting an anomaly in a flowing stream includes a set of blades rotatably suspended in the flowing stream and aligned with a normal flow direction of the flowing stream. The blades are configured to rotate at one rate when the anomaly is present in the flowing stream and to rotate at a different rate when the anomaly is absent from the flowing stream. A device is prescribed for measuring rate of rotation and rotation direction of the blades.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: August 27, 2002
    Inventors: Stephen T. Stark, Stephen H. Caldwell
  • Patent number: 6439326
    Abstract: A drill bit including a roller cone and fixed cutters positioned external to the roller cone and radially from the bit axis of rotation. The roller cone is located so that a drill diameter of the cone is substantially concentric with an axis of rotation of the bit. The fixed cutters can be made of tungsten carbide, polycrystalline diamond, boron nitride, or any other superhard material. The fixed cutters are positioned to either maintain the hole diameter drilled by the roller cone or to drill a larger diameter hole than the hole drilled by the roller cone. The single roller cone may be located in the center of a multi-cone bit arrangement or in the center of a PDC bit to assist in drilling the center of a wellbore. The single roller cone may be used to form a bi-center bit in combination with a reaming section. The single roller cone may also be located on an independent sub that is removably attached to the bit body.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: August 27, 2002
    Assignee: Smith International, Inc.
    Inventors: Sujian Huang, Chris E. Cawthorne
  • Patent number: 6441595
    Abstract: A device for automatically providing variable resistance includes a comparator for comparing a reference voltage to an operating voltage, a first switch operatively coupled to the comparator, a first resistor operatively coupled with the first switch in a series connection between a pull-up voltage and a signal line, a second switch operatively coupled to the comparator, and a second resistor operatively coupled in a series connection with the second switch between the pull-up voltage and the signal line. The first switch selectively electrically enables the connection between the pull-up voltage and the signal line through the first resistor based on the comparison between the reference voltage and the operating voltage and the second switch selectively electrically enables the connection between the pull-up voltage and the signal line through the second resistor based on the comparison between the reference voltage and operating voltage.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Gerald R. Pelissier, David S. Hwang
  • Patent number: 6441640
    Abstract: A circuit for regulating resonance in a micro-chip has been developed. The circuit includes micro-chip supply voltage and a ground voltage, and a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: August 27, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude R. Gauthier, Brian Amick, Tyler J. Thorp, Richard L. Wheeler
  • Patent number: 6435570
    Abstract: A resin pipe joint comprising a tapered flare portion (10a) formed on a pipe (10), an inclined portion (11a) formed internally of a joint body (11), an annular member (12) having inner peripheral surface fitted on the pipe (10) and the outer peripheral surface inserted in the joint body and formed at the end with a tapered chamfered portion (12a), and a pipe clamping member (13) threadedly fitted to the joint body (11). The pipe clamping member (13) being threadedly fitted to the joint body causes the chamfered portion (12a) of the annular member to pressure-contact the flare portion (10a) of the pipe and the flare portion of the pipe to pressure-contact the inclined portion in the interior of the joint body, whereby the clamping force can be concentrated on the flare portion of the pipe, so that a high sealing capability between the pipe and the joint body is obtained.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: August 20, 2002
    Assignee: Toho Kasei Co., Ltd.
    Inventors: Masahide Kato, Noboru Tamaki, Hideo Shibahara
  • Patent number: 6436737
    Abstract: A method for reducing soft error rates in semiconductor devices includes adding an isotopically enriched 11B compound during the manufacture of a semiconductor device. Such isotopically enriched 11B compounds include orthoborates (BOR3), acyl borates (B(OCOR)3), peroxo borates (OOR)3, boronic acids (RB(OH)2), boron halides, boron hydrides, inorganic boranes, amine boranes, aminoboranes, carboranes, and borazines, where R is an alkyl group. Disclosed uses include adding between 1% to 100% of the isotopically enriched 11B compound to an underfill material in flip-chip assembly; adding between 1% to 100% of the isotopically enriched 11B compound to an encapsulent; and adding between 1% to 100% of the isotopically enriched 11B compound to an adhesive.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: August 20, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Deviprasad Malladi
  • Patent number: 6435329
    Abstract: A movable table is insertably and withdrawably mounted on a casing. A depositing/dispensing mechanism for discriminating the note type and genuineness of a note deposited at the entrance of a conveyance path for conveying the note, feeding the note to a storing end corresponding to the discrimination result, and dispensing note(s) from its storing end by a specified input operation is mounted on the movable table. A controller for calculating a balance by detecting the depositing/dispensing of the notes is also provided. The depositing/dispensing mechanism includes a first mechanism for holding the deposited and dispensed notes before being calculated for the balance and a second mechanism for holding the deposited and dispensed notes after being calculated for the balance. The first and second mechanisms are provided at front and rear sides of the movable table with respect to a drawing direction, respectively.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: August 20, 2002
    Assignee: Nihon Kinsel Kikai Kabushiki Kaisha
    Inventors: Isao Amari, Hiroyuki Oiyama, Ikugo Mitsui
  • Patent number: 6430885
    Abstract: A fastened structure wherein flat siding boards such as ceramic siding boards are fastened to the side of a building by making use of a fastening member. A first engaging members each having an engaging groove and an engaging hook are attached to the side of a building at predetermined intervals “d”. On the other hand, the siding board is provided on the rear surface thereof with a number of a second engaging members each having an engaging projection which is adapted to be engaged with the engaging hook of the first engaging member. The siding boards can be fastened in multistage vertically to the side of the building by pressing the siding board onto the side of a building so as to cause the first engaging member to engage with the second engaging member.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: August 13, 2002
    Assignee: Nichiha Corporation
    Inventor: Hiroshi Ito
  • Patent number: 6431107
    Abstract: A floating offshore structure has a buoyant hull with sufficient fixed ballast to place the center of gravity of the floating structure below the center of buoyancy of the hull. A support structure coupled to an upper end of the hull supports and elevates a superstructure above the water surface. A soft tendon is attached between the hull and the seafloor. A vertical stiffness of the soft tendon results in the floating structure having a heave natural period of at least twenty seconds.
    Type: Grant
    Filed: April 15, 1999
    Date of Patent: August 13, 2002
    Assignee: Novellant Technologies, L.L.C.
    Inventor: Steven M. Byle
  • Patent number: 6427577
    Abstract: A load bearing apparatus includes a first container having enclosed ends and at least one expansion segment. The expansion segment includes a first cylinder and a second cylinder of diameter smaller than the first cylinder disposed along a longitudinal axis of the first cylinder. An elastomer seal is connected between the first and second cylinders to form a fluid tight seal between the cylinders. The elastomer seal further permits translation of the first cylinder with respect to the second cylinder in a direction along the longitudinal axis of the first cylinder.
    Type: Grant
    Filed: May 10, 1999
    Date of Patent: August 6, 2002
    Assignee: Novellant Technologies, LLC
    Inventors: James J. Lee, Steven M. Byle, John C. Montague
  • Patent number: 6429722
    Abstract: A method of reducing the noise of a clock signal distribution system for a flip-flop based circuit has been develop. The method first inputs a synchronized clock signal into a noise reduction circuit. The noise reduction circuit then begins to store charge upon receipt of the clock signal. Finally, the noise reduction circuit dumps the charge onto the system power grid at an appropriate time in conjunction with the clock signal.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 6, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Brian W. Amick, Claude R. Gauthier
  • Patent number: 6430067
    Abstract: A method and apparatus for a voltage multiplier is disclosed that includes a first stage for receiving an input voltage and a first control signal; inverting the first control signal to produce a second control signal; and outputting a first output voltage and the second control signal. The voltage multiplier also includes a second stage for receiving the first output voltage and the second control signal; and outputting a third output voltage. The first output voltage is higher than the input voltage and the second output voltage is higher than the first output voltage.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: August 6, 2002
    Assignee: Sun Microsystems, Inc.
    Inventor: Lan Lee
  • Patent number: 6427455
    Abstract: A cooling device is disclosed capable of reducing the amount of frost deposited on a cooling coil (7), wherein cooling fans (8a, 8b) are disposed at the front of the cooling coil (7), most of the flowing air discharged into a cooling chamber is discharged again into the cooling chamber by the cooling fans (8a, 8b) without being returned to the cooling coil (7), dry cooling air in the cooling coil (7) is sucked from the rear of the cooling fans (8a, 8b) and discharged into the cooling chamber, an air volume corresponding to the volume of sucked air passed through the cooling coil (7) is fed from the cooling chamber to the cooling coil (7) through areas not occupied by the cooling fans (8a, 8b), and the air feeding speed is so set as to permit vapor generated in the cooling chamber to solidity until the vapor is brought into contact with the surface of the cooling coil (7).
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: August 6, 2002
    Assignee: Light Shoki Kabushiki Kaisha
    Inventor: Yasuo Furubayashi
  • Patent number: 6426652
    Abstract: A method and apparatus for performing logic operations using dual-edge triggered dynamic logic families is provided. Further, a method for performing logic operations using a self-resetting mechanism within dual-edge triggered dynamic logic blocks is provided. Further, a dual-edge triggered dynamic circuit that maintains a duty cycle of an input signal at its output is provided. Further, a method for providing a buffer mechanism for clock distribution purposes is provided.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: July 30, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: David J. Greenhill, Pradeep Trivedi
  • Patent number: 6425477
    Abstract: A substrate conveyance system for transporting a substrate from a substrate source to either one of a plurality of substrate destinations. The substrate conveyance system is characterized by a combination comprising a first transfer module including substrate holding means for holding the substrate thereon and for changing orientation of the substrate, and a first housing surrounding the substrate holding means; and a second transfer module including a second housing which can be connected with the first housing, and transfer means in the second housing for transferring the substrate to or from said substrate holding means in the first housing which is connected with the second housing. Efficient interbay or intrabay transportation of substrates is enabled by arranging the combinations in a checkerboard form. In the arrangement, the combination is used as the minimum unit.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: July 30, 2002
    Inventor: Yasuto Karasawa
  • Patent number: 6425544
    Abstract: A taping technology capable of restraining an ill-wound state of a tape is disclosed. Chucking members of a leading chuck and chucking members of a trailing chuck have widths narrow enough to enter between flange members of a bobbin, and are therefore capable of grasping leading and trailing ends of the tape till the chucking members get close to a wire member wound on a cylindrical member, whereby disordered states at the leading and trailing ends of the tape can be restrained as much as possible and an ill-wound state of the tape can be therefore restrained.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: July 30, 2002
    Assignee: Tanaka Seiki Co., Ltd.
    Inventor: Kyoji Takeda