Abstract: A method for detecting a leak in a drill string valve used when drilling a subsea well. The method comprises measuring a first inlet pressure at a subsea mudlift pump while a subsea mudlift pump and a surface pump are operating and before a well is fully shut-in and measuring a second inlet pressure at the subsea mudlift pump after the mudlift pump and the surface pump are shut down and after the well is fully shut-in. The first and second subsea mudlift pump inlet pressure measurements are then compared, and a check is performed to determine if the subsea mudlift pump inlet pressure has increased by an amount greater than an estimated annular friction pressure.

Abstract: In a structure including a voltage control circuit 1 for changing a voltage control signal 14 to control an oscillation amplitude of a transistor Q1 for oscillation, thereby stabilizing a voltage of a secondary output 13, there are provided a load suppressing circuit 5 for restricting a lower limit of a load impedance of a secondary coil L2 to prevent the oscillation of the transistor Q1 for oscillation from being stopped when the secondary output 13 is short-circuited, and an intermittent control circuit 2 for repeating an operation for reducing a voltage of the voltage control signal 14 to stop the oscillation when detecting a short circuit of a load and for raising the voltage of the voltage control signal 14 to restart the oscillation after stopping the oscillation.

Abstract: A method for reducing power supply noise in the power supply system of a delay locked loop has been developed. The method includes powering up a delay locked loop and inserting a shunting resistance across the power supply terminals. The shunting resistance is inserted in parallel with the delay locked loop.

Abstract: A single-input/dual output sense amplifier includes cross-coupled transistors connected to a reference voltage; a first input transistor and a second input transistor connected to the cross-coupled transistors, wherein the first input transistor is coupled to a single input bit-line and the second input transistor is coupled to a reference voltage; an inverter receiving the input bit-line signal and outputting a complement of the input bit-line signal; a control circuit coupled to the second input transistor and receiving the complement of the input bit-line signal, wherein the cross-coupled transistors produce dual differential outputs.

Abstract: A memory device testing apparatus for testing a memory device (62) has a failure analysis memory unit (80) which includes: a data storing memory (12), in which fail data (26) output from a comparator (70) is written to an address corresponding to an address of a failure spot in the memory device (62), and a compact memory (14) in which failure information, which indicates that there is a failure spot in the memory device (62), is written based on the fail data (26) that was previously written to the data storing memory (12).

Abstract: A conventional data shared system using a plurality of processing nodes and data storage units in a storage area network using SAN OS was a volume-level locking or a file-system-level locking through one limited server. A locking system for SAN proposed this time is one that is a file-system-level locking and creates no single point of failure. Namely, the locking system is incorporated into each storage unit of Storage Area Network to run software. As a result, the storage unit is converted to an intelligent form and an acceptor (1) for a first protocol and an acceptor (2) for a second protocol coexist. This allows the acceptor (1) to perform a locking mechanism and the acceptor (2) to perform data transfer, so that the locking system that is a file system level locking and that creates no single point of failure can be realized. The plurality of protocols is thus used so as to execute data control and data transfer efficiently.

Abstract: A pin electronics, which inputs and outputs signal from and to an input/output pin of an electric part, provided in a testing apparatus that tests the electric part; including: a current source which outputs desired electric current; a first voltage generator which generates a desired voltage; and a diode bridge, which is connected to each of the current source, the first voltage generator, and the input/output pin of the electric part, that provides the desired electric current to the electric part and provides the desired voltage to the electric part; wherein: the first voltage generator has a current measuring unit that measures an electric current, which is input from the first voltage generator to the diode bridge.

Abstract: A system for minimizing the effect of clock skew in a precharge circuit includes a switch coupled between an input to the precharge circuit and a global bitline; and a control circuit coupled to a precharge component and the switch. The control circuit determines whether the switch and the precharge component are activated and the control circuit receives feedback from the switch. A method of minimizing the effect of clock skew in a precharge circuit includes controlling whether an input signal outputting a first signal and a second signal from the precharge circuit; controlling the outputting of the second signal from the precharge circuit based on a clock signal, a select signal, and a dynamic signal.

Abstract: A pattern generator that generates a test pattern used for testing an electric part including: a pattern memory that stores test pattern information, which defines the test pattern; a vector memory that stores a vector instruction, which indicates an order for reading out the test pattern information from the pattern memory; an address expansion unit that generates an address of the test pattern information in the pattern memory according to the vector instruction stored in the vector memory; an interruption pattern memory that stores interruption test pattern information, which defines the test pattern during a predetermined interruption process; an interruption vector memory, which is different from the vector memory, that stores an interruption vector instruction which indicates an order for reading out the interruption test pattern information from the interruption pattern memory; an interruption address expansion unit that generates an address of the interruption test pattern information according to th

Abstract: A system for minimizing the effect of clock skew in a bit line write driver includes a first control circuit coupled to the bit line write driver; and a second control circuit coupled to the bit line write driver. The bit line write driver outputs a first output signal and a second output signal. A method of minimizing the effect of clock skew in a bit line write driver includes outputting a first signal and a second signal from the bit line write driver; controlling the outputting of the second signal from the bit line write driver based on a feedback of the first signal; and controlling the outputting of the first signal from the bit line write driver based on feedback of the second signal.

Abstract: A control circuit 10 inputs a maximum value, which is read out of a resistor 22, to one of the input terminals of a comparator 14 by providing the maximum value to a D/A convertor 18 through a latch 16. The electric potential V, which is an object to be tested, is input to another input terminal of the comparator 14 through a hold circuit 12. The comparator 14 judges the magnitude of the value of the electric potential V by referring to the maximum value and outputs to the control circuit 10. The same operation is also performed for the minimum value. The pass/fail judgement is performed for judging whether the value of the electric potential V is within an allowable range by the comparison with the maximum value and the minimum value. Furthermore, the control circuit 10 performs an A/D conversion of the electric potential V by reading out data D1-Dn from the resistor 20 one after another to gradually change the reference of a comparison.

Abstract: In an apparatus and a process for preparing a flock-air mixture which is fed by a pulping device through a feed conduit to a flock-laying device for forming an absorbent pad, the feed conduit includes a dispersing device for loosening up lumps of flock within the mixture. To achieve a high level of efficiency in loosening the flock lumps, as independently as possible of the through-put of the mixture through the feed conduit, the dispersing device is in the form of a pneumatic dispersing device which loosens up the lumps by accelerating the mixture with lumps therein to cause the lumps to burst or tear apart.

Abstract: Method and apparatus for testing a semiconductor device having an A-D converting unit, capable of generating a highly accurate test waveform of high speed. The semiconductor testing apparatus includes: a first waveform generating unit which generates a first waveform having a predetermined waveform component; a second waveform generating unit which generates a second waveform having a known waveform component; a waveform synthesizing unit which generates a composite waveform by synthesizing the first waveform and the second waveform; a processing unit which processes to remove an effect of the second waveform from an output value; and a comparator which judges based on the first waveform and the output value processed by the processing unit.

Abstract: A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

Abstract: A method for constructing a latch mapping between a first level description and a second level description of a digital system, wherein the first level description and the second level descriptions identify components in the digital system using a predefined naming convention, is provided. The method includes identifying first latch components in the first level description and, for each identified first latch component, storing a first string comprising a selected property of the first latch component in a first storage. The method further includes identifying second latch components in the second level description and, for each second latch component, storing a second string comprising a selected property of the second latch component in a second storage. The method further includes generating a latch mapping by matching the first strings in the first storage with the second strings in the second storage.

Abstract: A substrate for detecting base sequences that comprises a transparent support, a thin metal film formed on one side of the transparent support, and a self-assembled monolayer with a nonionic aromatic compound being an intercalator of nucleic acid polymers dispersed over the surface formed on the metal film. The substrate is manufactured, for example, by immersing a transparent support with a thin gold film formed on one side in a solution that contains a disulfide (S—S) compound containing anthracene for the intercalator of nucleic acid polymers form on the metal film. A nucleic acid polymer (probe or target) is immobilized to the monolayer of the substrate, another nucleic acid polymer (target or probe) is hybridized to the nucleic acid polymer immobilized to the monolayer, and the results of the hybridization can be detected by the Surface Plasmon Resonance method after washing.

Abstract: A current measuring method, which measures a device current flowing through a terminal of a semiconductor device including charging the capacitor which is connected between the terminal and an earth potential of the semiconductor device, up to a predetermined voltage; setting the semiconductor device to be in active sate by applying a test pattern to the semiconductor device; measuring a potential of the capacitor at the terminal side after a predetermined test time has elapsed; and judging whether the device current is within a predetermined allowable range, based on the test time, capacitance of the capacitor, and the potential.

Abstract: A memory device testing apparatus has a pattern generator, which generates all of the signals used for a packet signal in one cycle, a pin data selector, which generates the packet signal by selecting some of the signals generated by the pattern generator and outputting the selected signals a plurality of times, a memory device socket, which can write test data into the memory device and read test data from the memory device, and a comparator, which compares expectation value data with test data.

Abstract: A process for producing a fluorine-containing acrylic or methacrylic polymer, comprises polymerizing a fluorine-containing acrylate or methacrylate in a solution phase formed of an organic solvent and dissolved therein a monomer containing a fluorine-containing acrylate or methacrylate having a polyfluoroalkyl group having 6 to 16 carbon atoms. A non-halogen type solvent is used as the organic solvent and the fluorine-containing acrylate or methacrylate is so polymerized that a polymer-containing liquid phase comprised of the fluorine-containing acrylic or methacrylic polymer formed with progress of polymerization and the organic solvent is separated from the solution phase. This process enables production of a fluorine-containing acrylic or methacrylic polymer having a fluorine monomer in a high proportion by the use of a commonly available general-purpose solvent, without using any fluorine type solvent.

Abstract: An electrostatic microrelay is disclosed. The electrostatic microrelay includes a fixed substrate having a fixed electrode and a fixed terminal on its upper surface and a moveable substrate having a moveable electrode and a moveable terminal on its lower surface. The moveable substrate is elastically supported by a support member that is disposed between the fixed substrate and the moveable substrate in a manner that the lower surface of the moveable substrate faces the upper surface of the fixed substrate at a certain distance. A protrusion is provided on the upper surface of the fixed substrate or the lower surface of the moveable substrate. The protrusion has a certain height.