Patents Represented by Attorney Saile Ackerman LLC
  • Patent number: 8345383
    Abstract: A non-conformal integrated side shield structure is disclosed for a PMR write head wherein the sidewalls of the side shield are not parallel to the pole tip sidewalls. Thus, the side gap distance between the leading pole tip edge and side shield is different than the side gap distance between the trailing pole tip edge and side shield. As a result, there is a reduced side fringing field and improved overwrite performance. The side gap distance is constant with increasing distance from the ABS along the main pole layer. A fabrication method is provided where the trailing shield and side shield are formed in the same step to afford a self-aligned shield structure. Adjacent track erasure induced by flux choking at the side shield and trailing shield interface can be eliminated by this design. The invention encompasses a tapered main pole layer in a narrow pole tip section.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 1, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Cherng-Chyi Yan, Feiyue Li, Shiwen Huang, Jiun-Ting Lee, Yoshitaka Sasaki
  • Patent number: 8343777
    Abstract: Detection of magnetic beads at temperature below room temperature can increase the signal level significantly as compared to the same detection when performed at room temperature. Additional improvement is obtained if the beads are below 30 nm in size and if deviations of bead size from the median are small. A preferred format for the beads is a suspension of super-paramagnetic particles in a non-magnetic medium.
    Type: Grant
    Filed: February 10, 2012
    Date of Patent: January 1, 2013
    Assignee: Headway Technologies, Inc.
    Inventor: Yuchen Zhou
  • Patent number: 8345481
    Abstract: A NOR flash nonvolatile memory or reconfigurable logic device has an array of NOR flash nonvolatile memory circuits that includes charge retaining transistors serially connected in a NAND string such that at least one of the charge retaining transistors functions as a select gate transistor to prevent leakage current through the charge retaining transistors when the charge retaining transistors is not selected for reading. The topmost charge retaining transistor's drain is connected to a bit line parallel to the charge retaining transistors and the bottommost charge retaining transistor's source is connected to a source line and is parallel to the bit line. The charge retaining transistors are programmed and erased with a Fowler-Nordheim tunneling process.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: January 1, 2013
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Fu-Chang Hsu, Hsing-Ya Tsao
  • Patent number: 8345388
    Abstract: In a read-write head, the shields can serve as magnetic flux conductors for external fields, so that they direct a certain amount of flux into the recording medium. This problem has been overcome by the addition to the shields of a pair of tabs located at the edges closest to the ABS. These tabs serve to prevent flux concentrating at the edges so that horizontal fields at these edges are significantly reduced. Said tabs need to have aspect ratios of at least 2 and may be either triangular or rectangular in shape. Alternatively, the tabs may be omitted and, instead, outer portions of the shield's lower edge may be shaped so as to slope upwards away from the ABS.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: January 1, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Lijie Guan, Moris Dovek
  • Patent number: 8339754
    Abstract: An insertion layer is provided between an AFM layer and an AP2 pinned layer in a GMR or TMR element to improve exchange coupling properties by increasing Hex and the Hex/Hc ratio without degrading the MR ratio. The insertion layer may be a 1 to 15 Angstrom thick amorphous magnetic layer comprised of at least one element of Co, Fe, or Ni, and at least one element having an amorphous character selected from B, Zr, Hf, Nb, Ta, Si, or P, or a 1 to 5 Angstrom thick non-magnetic layer comprised of Cu, Ru, Mn, Hf, or Cr. Preferably, the content of the one or more amorphous elements in the amorphous magnetic layer is less than 40 atomic %. Optionally, the insertion layer may be formed within the AP2 pinned layer. Examples of an insertion layer are CoFeB, CoFeZr, CoFeNb, CoFeHf, CoFeNiZr, CoFeNiHf, and CoFeNiNbZr.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: December 25, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Hui-Chuan Wang, Tong Zhao, Min Li
  • Patent number: 8339751
    Abstract: A method is disclosed for forming a magnetic shield in which all domain patterns and orientations are stable and which are consistently repeated each time said shield is exposed to an initialization field. The shield is given a shape which ensures that all closure domains can align themselves at a reduced angle relative to the initialization direction while still being roughly antiparallel to one another. Most, though not all, of these shapes are variations on trapezoids.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: December 25, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Glen Garfunkel, Moris Dovek, Kenichi Takano, Joseph Smyth, Yuchen Zhou
  • Patent number: 8337676
    Abstract: A high performance TMR sensor is fabricated by incorporating a tunnel barrier having a Mg/MgO/Mg configuration. The 4 to 14 Angstroms thick lower Mg layer and 2 to 8 Angstroms thick upper Mg layer are deposited by a DC sputtering method while the MgO layer is formed by a NOX process involving oxygen pressure from 0.1 mTorr to 1 Torr for 15 to 300 seconds. NOX time and pressure may be varied to achieve a MR ratio of at least 34% and a RA value of 2.1 ohm-um2. The NOX process provides a more uniform MgO layer than sputtering methods. The second Mg layer is employed to prevent oxidation of an adjacent ferromagnetic layer. In a bottom spin valve configuration, a Ta/Ru seed layer, IrMn AFM layer, CoFe/Ru/CoFeB pinned layer, Mg/MgO/Mg barrier, CoFe/NiFe free layer, and a cap layer are sequentially formed on a bottom shield in a read head.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: December 25, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Tong Zhao, Kunliang Zhang, Hui Chuan Wang, Yu-Hsia Chen, Min Li
  • Patent number: 8334681
    Abstract: A low dropout voltage regulator comprising a first output voltage regulation loop with a NMOS transistor as a pass element and a second output voltage regulation loop with a PMOS transistor as a pass element. The NMOS transistor is used for small current loads up to 1 mA, the PMOS transistor is used for higher current loads from 1 mA and up. A current sense buffer senses the current through the NMOS transistor and controls the gate of the PMOS transistor accordingly. Good load transient operation is achieved without the need of an external load capacitor.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: December 18, 2012
    Assignee: Dialog Semiconductor GmbH
    Inventor: Antonello Arigliano
  • Patent number: 8335105
    Abstract: By inserting a spin polarizing layer (typically pure iron) within the free layer of a MTJ or GMR memory cell, dR/R can be improved without significantly affecting other free layer properties such as Hc. Additional performance improvements can be achieved by also inserting a surfactant layer (typically oxygen) within the free layer.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: December 18, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Hui-Chuan Wang, Tong Zhao, Kunliang Zhang, Min Li
  • Patent number: 8334213
    Abstract: A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 18, 2012
    Assignee: MagIC Technologies, Inc.
    Inventor: Guomin Mao
  • Patent number: 8334147
    Abstract: A magnetic sensor for identifying small magnetic particles bound to a substrate includes a regular, planar orthogonal array of MTJ cells formed within or beneath that substrate. Each MTJ cell has a high aspect ratio and positions of stable magnetic equilibrium along an easy magnetic axis and positions of unstable magnetic equilibrium along a hard magnetic axis. By initializing the magnetizations of each MTJ cell in its unstable hard-axis position, the presence of even a small magnetic particle can exert a sufficient perturbative strayfield to tip the magnetization to its stable position. The magnetization change in an MTJ cell can be measured after each of two successive opposite polarity magnetizations of a bound particle and the presence of the particle thereby detected.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: December 18, 2012
    Assignee: MagIC Technologies, Inc.
    Inventor: Otto Voegeli
  • Patent number: 8335108
    Abstract: A nonvolatile memory structure with pairs of serially connected threshold voltage adjustable select transistors connected to the top and optionally to the bottom of NAND series strings of groups of the dual-sided charge-trapping nonvolatile memory cells for controlling connection of the NAND series string to an associated bit line. A first of the threshold voltage adjustable select transistors has its threshold voltage level adjusted to a first threshold voltage level and a second of the threshold voltage adjustable select transistors adjusted to a second threshold voltage level. The pair of serially connected threshold voltage adjustable select transistors is connected to a first of two associated bit lines. The NAND nonvolatile memory strings further is connected to a pair of serially connected threshold voltage adjustable bottom select transistors that is connected to the second associated bit line.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: December 18, 2012
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Peter Wung Lee, Fu-Chang Hsu
  • Patent number: 8331059
    Abstract: A bracket for a hard disc drive combining three separate functions, a ramp, a latch and a connector bracket into a single assembly. The bracket assembly, mounted with ramp and latch, secures and seals the electrical connector connecting the flexible printed circuit on the head side of the actuator. Traditionally, latches are on the coil side of the actuator. Moreover, the combination bracket improves manufacturability while reducing overall cost for the disc drive. The assembly can be purchased complete from a supplier.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: December 11, 2012
    Assignee: SAE Magnetics (HK) Ltd.
    Inventor: Stephen Ralph Viskochil
  • Patent number: 8329320
    Abstract: A laminated high moment film with a non-AFC configuration is disclosed that can serve as a seed layer for a main pole layer or as the main pole layer itself in a PMR writer. The laminated film includes a plurality of (B/M) stacks where B is an alignment layer and M is a high moment layer. Adjacent (B/M) stacks are separated by an amorphous layer that breaks the magnetic coupling between adjacent high moment layers and reduces remanence in a hard axis direction while maintaining a high magnetic moment and achieving low values for Hch, Hce, and Hk. The amorphous material layer may be made of an oxide, nitride, or oxynitride of one or more of Hf, Zr, Ta, Al, Mg, Zn, Ti, Cr, Nb, or Si, or may be Hf, Zr, Ta, Nb, CoFeB, CoB, FeB, or CoZrNb. Alignment layers are FCC soft ferromagnetic materials or non-magnetic FCC materials.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: December 11, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Min Li, Min Zheng, Fenglin Liu, Xiaomin Liu
  • Patent number: 8330532
    Abstract: Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: December 11, 2012
    Assignee: Dialog Semiconductor GmbH
    Inventors: Ludmil Nikolov, Carlos Calisto
  • Patent number: 8331150
    Abstract: A nonvolatile SRAM circuit has an SRAM cell and one or two FLOTOX EEPROM cells connected to the data storage terminals of the SRAM cell. In programming to a first data level, the threshold voltage of a FLOTOX EEPROM transistor is brought to a programmed voltage level greater than a read voltage level and erasing to a second data level, the threshold voltage of the FLOTOX EEPROM transistor is brought to an erased voltage level less than the read voltage level. The nonvolatile SRAM array provides for restoring data to an SRAM cell from a FLOTOX EEPROM memory cell(s) at a power initiation and storing data to the FLOTOX EEPROM memory cell(s) to the SRAM cell at power termination. A power detection circuit for providing signals indicating power initiation and power termination to instigate restoration and storing of data between an SRAM cell and a FLOTOX EEPROM cell(s).
    Type: Grant
    Filed: January 5, 2009
    Date of Patent: December 11, 2012
    Assignee: Aplus Flash Technology, Inc.
    Inventors: Fu-Chang Hsu, Peter Wung Lee
  • Patent number: 8325449
    Abstract: Plasma nitridation, in place of plasma oxidation, is used for the formation of a CCP layer. Al, Mg, Hf, etc. all form insulating nitrides under these conditions. Maintaining the structure at a temperature of at least 150° C. during plasma nitridation and/or performing post annealing at a temperature of 220° C. or higher, ensures that no copper nitride can form. Additionally, unintended oxidation by molecular oxygen of the exposed magnetic layers (mainly the pinned and free layers) is also avoided.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: December 4, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Min Li, Yue Liu
  • Patent number: 8324969
    Abstract: A variable gain amplifier device (100) with improved gain resolution is achieved. The device includes a programmable gain amplifier (PGA) (110), an analog-to-digital converter (ADC) (160), an automatic level control (ALC) algorithm means (176), and a delta-sigma modulator (180). The PGA (110) is capable to receive and to amplify an analog input signal (154) to thereby generate an analog output signal (164). The PGA (110) includes an amplifier (160) and a switchable resistor network (120). The ADC (170) is coupled to the PGA (110) and is capable to convert the analog output signal (164) to a digital signal (174). The ALC algorithm means (176) is coupled to the ADC (170) and is capable to generate a control code (178) by processing the digital signal (174). The delta-sigma modulator (186) is coupled to the ALC algorithm means (186) and is capable to generate a pulse-density modulated (PDM) signal (182) by processing the control code (178).
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: December 4, 2012
    Assignee: Dialog Semiconductor GmbH
    Inventors: Sebastian Loeda, Alisdair Muir
  • Patent number: 8324698
    Abstract: A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.
    Type: Grant
    Filed: January 4, 2011
    Date of Patent: December 4, 2012
    Assignee: MagIC Technologies, Inc.
    Inventors: Tom Zhong, Chyu-Jiuh Torng, Rongfu Xiao, Adam Zhong, Wai-Ming Johnson Kan, Daniel Liu
  • Patent number: 8325448
    Abstract: The pinning field in an MR device was significantly improved by using the Ru 4A peak together with steps to minimize interfacial roughness of the ruthenium layer as well as boron and manganese diffusion into the ruthenium layer during manufacturing. This made it possible to anneal at temperatures as high as 340° C. whereby a high MR ratio could be simultaneously achieved.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 4, 2012
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Shengyuan Wang, Tong Zhao, Min Li, Hui-Chuan Wang