Abstract: An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.

Abstract: A process for manufacturing a high performance MTJ it is described: A first cap layer of NiFeHf is deposited on the free layer, followed by a second cap layer of Ru on Ta. The device is then heated so that oxygen trapped in the free layer diffuses into the NiFeHf layer, thereby sharpening the interface between the tunnel barrier layer and the free layer.

Abstract: A TAMR (Thermal Assisted Magnetic Recording) write head uses the energy of optical-laser generated plasmons in a magnetic core plasmon antenna to locally heat a magnetic recording medium and reduce its coercivity and magnetic anisotropy. To enable the TAMR head to operate most effectively, the maximum gradient and value of the magnetic recording field should be at a point of the magnetic medium that is as close as possible to the point being heated. In addition, the coupling between the optical mode and the plasmon mode should be efficient so that maximum energy is transmitted to the medium. The present invention achieves both these objects by surrounding the magnetic core of a plasmon antenna by a variable thickness plasmon generating layer, whose thinnest and shortest portion is at the ABS end of the TAMR head and whose thickest and longest portion efficiently couples to the optical mode of a waveguide to produce a plasmon.

Abstract: The present invention provides a novel read method of twin MONOS metal bit or diffusion bit structure for high-speed application. In a first embodiment of the present invention, the alternative control gates are set at the same voltage. In a second embodiment of the present invention, all the control gates are set at the operational voltage from the beginning. In both embodiments, the bit line and word gate are used to address the selected memory cell.

Abstract: A cladding structure for a conductive line used to switch a free layer in a MTJ is disclosed and includes two cladding sidewalls on two sides of the conductive line, a top cladding portion on a side of the conductive line facing away from the MTJ, and a highly conductive, non-magnetic spacing control layer formed between the MTJ and conductive line. The spacing control layer has a thickness of 0.02 to 0.12 microns to maintain the distance separating free layer and conductive line between 0.03 and 0.15 microns. The spacing control layer is aligned parallel to the conductive line and contacts a plurality of MTJ elements in a row of MRAM cells. Half-select error problems are avoided while maintaining high write efficiency. A spacing control layer may be formed between a word line and a bottom electrode in a top pinned layer or dual pinned layer configuration.

Abstract: A composite seed layer that reduces the shield to shield distance in a read head while improving Hex (exchange coupling field) and Hex/Hc (Hc=coercivity) is disclosed and has a SM/A/SM/B configuration in which the SM layers are soft magnetic layers, the A (amorphous) layer is made of at least one of Co, Fe, Ni, and includes one or more amorphous elements, and the B layer is a buffer layer that contacts the AFM (anti-ferromagnetic) layer in the spin valve. The SM/A/SM stack together with the S1 (bottom) shield forms an effective shield such that the buffer layer serves as the effective seed layer while maintaining a blocking temperature of 260° C. in the AFM layer. The lower SM layer may be omitted. Examples of the amorphous layer are CoFeB, CoFeZr, CoFeNb, CoFeHf, CoFeNiZr, CoFeNiHf, and CoFeNiNbZr while the buffer layer may be Cu, Ru, Cr, Al, or NiFeCr.

Abstract: Systems and methods for switched-mode amplifiers having improved harmonic distortion are disclosed. High order in-band filtering is enabled without undue trade-off of distortion due to intermodulation/aliasing. A pre-modulation block is introduced, deployed between a loop filter block and a pulse-width modulation block, performing uniform pulse-width modulation. The pre-modulation block attenuates/removes amplitude dependent high frequency ripples before pulse-width modulation. The pre-modulation block in conjunction with the pulse-width modulation block performs double sampling of the input signals.

Abstract: A circuit and a method are provided for suppressing the pop and click noise during the power on and power off of Class D amplifiers. The technique also suppresses pops and clicks when the Class D amplifier enters or exits standby mode. A duplicate feedback network is used to establish the stable operating points, including offsets in the Class D circuit without turning on the outputs. The technique works by gradually propagating or dissipating the offset through the signal path of a Class D amplifier by swapping the differential outputs using switches to suppress pops and clicks when starting up and shutting down the amplifier.

Abstract: A circuit and methods eliminating production related luminance variations of electronic display applies to all display technologies that require gamma adjustment or also adjustment of other display parameters e.g. brightness or contrast as e.g. LCD or OLED display modules are disclosed. This is performed by individual trimming of the display driver's gamma curve One alternative is that an end-user has access to a non-volatile memory and replaces the factory default settings of the gamma curve with individual settings. Another alternative is to load gamma curve parameters from the non-volatile memory to gamma control registers and perform tweaking of the gamma curve from these control registers on top of the factory default settings in the non-volatile memory.

Abstract: A method and circuit are given, to realize a Bit-Line Sense Amplifier with Data-Line Bit Switch (BS) pass transistors for Random Access Memory (RAM) products as Integrated Circuit (IC) fabricated in CMOS technology with optimized operating characteristics of said RAM product with respect to good write stability and high write speed and wherein the layout area of the BS FET-switches and thus also the die size is minimized. This is achieved by using a two thickness technique of oxide layers for crucial internal circuit parts of the chip.

Abstract: A self-trim circuit provides a technique to trim a CUT (circuit under trim) using a LSB offset to determine the best digital value to trim the CUT. The self-trim circuit is also used to self-test the digital and analog portions of the self-trim circuitry, whereby the existence of a digital stuck at fault condition is detected. A state machine controls a digital stack to couple digital trim data to the CUT and read the output of a comparator circuit that signifies when a proper digital trim value has been used. Thereafter the proper digital trim value is stored into a nonvolatile memory.

Abstract: A nonvolatile trap charge storage cell selects a logic interconnect transistor uses in programmable logic applications, such as FPGA. The nonvolatile trap charge element is an insulator located under a control gate and above an oxide on the surface of a semiconductor substrate. The preferred embodiment is an integrated device comprising a word gate portion sandwiched between two nonvolatile trap charge storage portions, wherein the integrated device is connected between a high bias, a low bias and an output. The output is formed by a diffusion connecting to the channel directly under the word gate portion. The program state of the two storage portions determines whether the high bias or the low bias is coupled to a logic interconnect transistor connected to the output diffusion.

Abstract: A STT-RAM MTJ is disclosed with a MgO tunnel barrier formed by a NOX process, a CoFeB/FeSiO/CoFeB composite free layer with a middle nanocurrent channel layer to minimize Jc0, and a Ru capping layer to enhance the spin scattering effect and increase dR/R. Good write margin is achieved by modifying the NOX process to afford a RA less than 10 ohm-?m2 and good read margin is realized with a dR/R of >100% by annealing at 330° C. or higher to form crystalline CoFeB free layers. The NCC thickness is maintained in the 6 to 10 Angstrom range to reduce Rp and avoid Fe(Si) granules from not having sufficient diameter to bridge the distance between upper and lower CoFeB layers. A FeSiO layer may be inserted below the Ru layer in the capping layer to prevent the Ru from causing a high damping constant in the upper CoFeB free layer.

Abstract: A MRAM structure is disclosed that includes a metal contact bridge (MCB) which provides an electrical connection between a MTJ top electrode and an overlying bit line. The MCB has a width greater than a MTJ top electrode and serves as an etch stop during bit line etching to prevent sub-trenches from forming adjacent to the top electrode and causing shorts. MCBs also prevent insufficient etching that causes open circuits. A MCB is preferably a metal, metal compound, or alloy such as Ta with low resistivity and high conductivity. The MCB layer is patterned prior to using a dual damascene process to form a bit line contacting each MCB and a bit line pad connection to a word line pad. MCB thickness is thin enough to allow a strong bit line magnetic field for switching a free layer and large enough to function as an efficient oxide etch stop.

Abstract: A system and method for measuring the modulation between a magnetic head and a magnetic storage medium, such as a disk, is disclosed. A magnetic read/write head is positioned above a magnetic storage medium at a given flying height. The magnetic read/write head reads a signal from the magnetic storage medium. A tester measures an alternating electric current between the magnetic read/write head through the slider and the magnetic storage medium. A computer may then calculate the modulation by the magnetic read/write head based on the alternating electric current. A DC voltage to the head may be applied to lower the flying height of the magnetic head.

Abstract: A sloped reader is disclosed that reduces skew between reader and written transitions in shingled writing. The reader is formed between surfaces of S1 and S2 shields that are aligned parallel to the sloped reader. A PMR writer is described that straightens transition curvature and reduces signal-to-noise ratio in shingled writing. In one embodiment, a symmetrical writer with a bowed trailing edge where two corners have a greater pole height than a center portion may be used for either right corner or left corner shingled writing. In a second embodiment, an asymmetrical writer is formed with a straight and sloped trailing edge such that the write corner has a greater pole height than the opposite corner on the trailing edge. The bowed angle in the symmetrical writer and slope angle in the asymmetrical writer is between 5 and 45 degrees and preferably between 10 and 30 degrees.

Abstract: A sensor array comprising a series connection of parallel GMR sensor stripes provides a sensitive mechanism for detecting the presence of magnetized particles bonded to biological molecules that are affixed to a substrate. The adverse effect of hysteresis on the maintenance of a stable bias point for the magnetic moment of the sensor free layer is eliminated by a combination of biasing the sensor along its longitudinal direction rather than the usual transverse direction and by using the overcoat stress and magnetostriction of magnetic layers to create a compensatory transverse magnetic anisotropy. By making the spaces between the stripes narrower than the dimension of the magnetized particle and by making the width of the stripes equal to the dimension of the particle, the sensitivity of the sensor array is enhanced.

Abstract: A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

Abstract: A scheme for forming a thin metal interconnect is disclosed that minimizes etch residues and provides a wet clean treatment for via openings. A single layer interlayer dielectric (ILD), BARC, and photoresist layer are successively formed on a substrate having a copper layer that is coplanar with a dielectric layer. In one embodiment, the ILD is silicon nitride with 100 to 600 Angstrom thickness. After a via opening is formed in a photoresist layer above the copper layer, a first RIE process including BARC main etch and BARC over etch steps is performed. Then a second RIE step transfers the opening through the ILD to uncover the copper layer. Photoresist and BARC are stripped with oxygen plasma and a low DC bias. Wet cleaning may involve a first ST250 treatment, ultrasonic water treatment, and then a third ST250 treatment. A bottom electrode layer may be deposited in the via opening.

Abstract: Circuits and methods to achieve a switch interface circuit for a single pole, single throw (SPST) momentary push-button switch consuming a few tens of nanoamps whilst the push-button switch is closed, having low impedance input path when the switch is open in order to eliminate RFI interference have been achieved. The two states of the push-button switch, open and closed, maintain a low impedance path to one of the power supplies. The supply current is zero when the switch is open and is minimized whilst the switch is closed. The asynchronous edge triggered detection of the switch event allows an extended switch open to closed transition operation.