Abstract: A method of sensing a data value stored at a resistance based memory is disclosed. The method includes receiving a data signal from a data cell. The data cell includes a resistance based memory element. A reference signal is received from a reference circuit. The reference circuit includes a resistance based memory element. The data signal is converted to a data output signal having a first frequency. The reference signal is converted to a reference output signal having a second frequency. A first output signal is generated when the first frequency exceeds the second frequency. A second output signal is generated when the second frequency exceeds the first frequency.

Abstract: A novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph are provided. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed to form a loop twice, once using a low degree variable nodes and once using a higher degree variable which is higher than the low degree variable node, where the higher degree variable node comprises a non-loop-closing edge. In one embodiment, the plurality of low degree variable nodes may have the same permutation on each edge.

Abstract: Systems, circuits and methods for software programmable logic using Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) technology are disclosed. Magnetic tunnel junction (MTJ) storage elements can be formed into input planes and output planes. The input planes and output planes can be coupled together to form complex arrays that allow for the realization of logic functions.

Abstract: Embodiments of the present disclosure use one or more gain stages to generate an output voltage representing whether a resistive memory element of a data cell stores a high data value or a low data value. In a particular embodiment, an apparatus includes a sensing circuit. The sensing circuit includes a first amplifier stage that is configured to convert a first current through a first resistive memory element of a memory cell into a first single-ended output voltage. A second amplifier stage is configured to amplify the first single-ended output voltage of the first amplifier stage to produce a second single-ended output voltage.

Abstract: A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions.

Abstract: A magnetic tunneling junction (MTJ) device and fabrication method is disclosed. In a particular embodiment, an apparatus is disclosed that includes an MTJ device. The MTJ device includes a barrier layer, a free layer, and a magnesium (Mg) capping layer. The free layer is positioned between the barrier layer and the magnesium (Mg) capping layer.

Abstract: Reliability and yield of MTJ devices is improved by reducing surface roughness in the MTJ layers of the MTJ devices. Surface roughness is reduced by reducing surface roughness of layers below the MTJ layers such as the bottom electrode layer. Planarizing the bottom electrode layer through chemical mechanical polishing or etch back of spin-on material before depositing the MTJ layers decreases surface roughness of the bottom electrode layer and the MTJ layers. Alternatively, a capping layer may be planarized before deposition of the bottom electrode layer and MTJ layers to reduce surface roughness in the capping layer, the bottom electrode layer, and the MTJ layers.

Abstract: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

Abstract: A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.

Abstract: A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device.

Abstract: A system and method to control a direction of a current applied to a magnetic tunnel junction is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier. The sense amplifier is coupled to a first path and to a second path. The first path includes a first current direction selecting transistor and the second path includes a second current direction selecting transistor. The first path is coupled to a bit line of the MTJ storage element and the second path is coupled to a source line of the MTJ storage element.

Abstract: In a particular embodiment, an apparatus is disclosed that includes at least one controllable energy consuming module and a prediction engine. The prediction engine includes detection logic configured to determine a historical usage pattern of the at least one controllable energy consuming module, prediction logic configured to create a prediction rule that predicts future usage of the at least one controllable energy consuming module based on the historical usage pattern, control logic configured to selectively control an energy level of the at least one controllable energy consuming module based on the prediction rule, and learning logic configured to update the prediction logic in response to detecting usage of the at least one controllable energy consuming module in a manner that differs from the usage predicted by the prediction rule.

Abstract: A multiple-port RAM circuit has a data-in line coupled to multiple bit lines and multiple bit line bars. The circuit also has multiple word lines. A memory cell is coupled to the bit lines, bit line bars, and word lines. The circuit further includes a controller than enables the word lines to substantially simultaneously write a value from the bit lines to the memory cell.

Abstract: A method, apparatus, and machine readable medium for processing a plurality of Z-vectors. Each Z-vector includes Z elements, and each element includes K bits. The Z-vectors correspond to a binary codeword, portions of which have a relationship to a plurality of transmission units. The Z-vectors are stored in a set of D memory arrays. Each memory array includes Z rows of memory locations. Each memory location corresponds to a different array column, and each array column corresponds to a different Z-vector. Each Z-vector identifies one column. A series of sets of control information is generated. Each set includes a transmission unit identifier, a Z-vector identifier, and a row identifier. For at least one set, P times K divided by D bits is read from each column identified by the Z-vector that is identified by the Z-vector identifier included in the set.

Abstract: A computer program for generating an H-tree for an integrated circuit design stored on a computer readable medium includes code to receive from a user a set of parameters to configure the H-tree. The parameters include a starting segment length and an ending segment length. The computer program also includes code to select a starting location in the integrated circuit design. The computer program further includes code to place an anchor H at the starting location. The computer program further includes code to recursively place child Hs on the H-tree based on the starting segment length and the ending segment length to create a fan-out with equal weight on each child H. The number of levels of the H-tree is calculated according to a rounded down integer equal to a binary logarithm of a quotient of the starting segment length divided by the ending length.

Abstract: Efficient coding and communication is accomplished by transmitting first and second sets of information using a relatively large transmission block including a plurality of minimum transmission units (MTUs), each MTU corresponding to a unique combination of resources. A first set of MTUs is used in conveying the first set of information, the first set including at least a majority of the MTUs in the transmission block. A second set of the MTUs is defined, e.g., selected, for use in conveying the second set of information, the second set of MTUs including less MTUs than the first set and at least some MTUs included in the first set. The first and second sets of information are communicated by transmitting at least some MTUs included in the first and the second sets of MTUs with the corresponding information modulated thereon.

Abstract: Methods and apparatus relating to communicating in a system including relay stations are described. Various described methods and apparatus are directed to improved performance and/or mitigating interference in relay station boundary areas. Relay station transmission power is controlled based on at least one of time or frequency such that a transmission power level for a frequency is varied in a predetermined manner with time or such that different transmission power levels are used for different carrier frequencies. Different adjacent relay stations are intentionally configured to use different transmission power levels for the same carrier and/or have different time varying transmission power level profiles for the same carrier. A relay station performs access terminal scheduling based on access terminal location with respect to relay station boundary regions and transmission power level information.

Abstract: Techniques for using at least one of omni-directional and directional antennas for communication are described. A station may be equipped antenna elements selectable for use as an omni-directional antenna or one or more directional antennas. The station may select the omni-directional antenna or a directional antenna for use for communication based on various factors such as, e.g., whether the location or direction of a target station for communication is known, whether control frames or data frames are being exchanged, etc.

Abstract: Improved pilot signal sequences which facilitate multiple channel quality measurements, e.g., through the use of different signal pilot transmission power levels, are described. In various implementations the transmitted pilot sequences facilitate determining the contribution of interference from other sectors of a cell using the same tones, e.g., in a synchronized manner, as the sector in which the pilot signal measurements are being made. To measure noise contributions from neighboring sectors a sector NULL pilot, e.g., a pilot with zero power, is transmitted in an adjacent sector at the same time a pilot signal with a pre-selected, and therefore known, non-zero power is transmitted in the sector where the received pilot signal measurement is made. To facilitate background noise measurements, a cell NULL is supported in some embodiments. In the case of a cell NULL, all sectors of a cell transmit a Null pilot, on a tone that is used to measure background noise.

Abstract: Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cells are disclosed. The bit cells include a source line formed in a first plane and a bit line formed in a second plane. The bit line has a longitudinal axis that is parallel to a longitudinal axis of the source line, and the source line overlaps at least a portion of the bit line.