Abstract: A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.

Abstract: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.

Abstract: A system and method of connecting a macro cell to a system power supply network is disclosed. In a particular embodiment, the method includes determining a distance of an edge of the macro cell from a power line or a ground line of the system power supply network. The method further includes selectively adding at least one line to the system power supply network.

Abstract: A sensing circuit is disclosed. The sensing circuit includes a first path including a first resistive memory device and a second path including a reference resistive memory device. The first path is coupled to a first split path including a first load transistor and to a second split path including a second load transistor. The second path is coupled to a third split path including a third load transistor and to a fourth split path including a fourth load transistor.

Abstract: A dual current switch detection circuit with selective activation is disclosed. In a particular embodiment, the switch detection circuit comprises an input node coupled to a switch to receive an input signal from the switch, a first current source coupled to the input node, a second current source coupled to the input node, and a detection circuit having an input coupled to the input node and an output coupled to the second current source to selectively activate the second current source.

Abstract: A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

Abstract: A semiconductor memory device includes address signal level shifters configured to transform a low level address signal into a higher level address signal. A decoder is configured to receive the higher level address signal and, in response, provide word line signals. Write drivers receive low level data input signals and configure bitlines in response to the received input. Memory cells are responsive to the word line signals and to the configured bit lines for storing data therein.

Abstract: A first device is configured to select and utilize a connection identifier (CID) for a peer-to-peer communication connection between the first device and a second device in a wireless communications network. The CID is selected from a predetermined set of a plurality of CIDs. Prior to selecting the connection identifier, the first device monitors a CID broadcast channel to determine whether the CID is being utilized by other nearby connections. If it is determined that the CID is being utilized by another connection in the proximity, a different (unused) CID is selected. A transmission request is transmitted to the second device using a first transmission resource unit within a traffic management channel slot, the first transmission resource unit being determined as a function of the selected CID. The first device transmits traffic data to the second device in a traffic channel slot corresponding to the traffic management channel slot.

Abstract: The present invention provides a method for establishing a secure channel between wireless devices. The method involves reducing the transmit power of the devices in conjunction with placing the devices in close proximity to one another. By reducing the transmit power, wireless communications between the devices cannot be detected by other devices beyond the short transmission range. The devices then generate and exchange encryption keys using the reduced-power transmissions in order to establish a secure, encrypted communications channel. Once the secure channel is established, the devices increase their transmit power back to normal operating levels, allowing them to be moved further apart while maintaining secure wireless communications.

Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.

Abstract: A method for forming a magnetic tunnel junction (MTJ) for magnetic random access memory (MRAM) using two masks includes depositing over an interlevel dielectric layer containing an exposed first interconnect metallization, a first electrode, a fixed magnetization layer, a tunneling barrier layer, a free magnetization layer and a second electrode. An MTJ structure including the tunnel barrier layer, free layer and second electrode is defined above the first interconnect metallization by a first mask. A first passivation layer encapsulates the MTJ structure, leaving the second electrode exposed. A third electrode is deposited in contact with the second electrode. A second mask is used to pattern a larger structure including the third electrode, the first passivation layer, the fixed magnetization layer and the first electrode. A second dielectric passivation layer covers the etched plurality of layers, the first interlevel dielectric layer and the first interconnect metallization.

Abstract: A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, the method includes depositing a capping material on a free layer of a magnetic tunneling junction structure to form the capping layer and oxidizing a portion of the capping material to form a layer of oxidized material.

Abstract: An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address spaces. Each bit cell of the N-dimension addressable memory includes a bit storage element, N word lines, and N bit lines.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: A level shifter has at least one of either a pull up or a pull down circuit. The circuit is made of electronic components with reliability limits less than a maximum signal level output by the level shifter. The level shifter also has a timing circuit coupled to at least on of either the pull up or pull down circuit. The timing circuit controls a time of application of an input signal to at least one of either the pull up or pull down circuit preventing a terminal to terminal signal level experienced by the electronic components exceeding the reliability limits.

Abstract: Systems, circuits and methods for controlling the word line voltage applied to word line transistors in Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) are disclosed. One embodiment is directed to a STT-MRAM including a bit cell having a magnetic tunnel junction (MTJ) and a word line transistor. The bit cell is coupled to a bit line and a source line. A word line driver is coupled to a gate of the word line transistor. The word line driver is configured to provide a word line voltage greater than a supply voltage below a transition voltage of the supply voltage and to provide a voltage less than the supply voltage for supply voltages above the transition voltage.

Abstract: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.

Abstract: Metal is deleted from portions of metal wires in an integrated circuit layout, based upon a width of the metal wires. Preliminary cutting forms having a length and a width are inserted with a first orientation in the portions of metal wire. It is determined if the width of each of the preliminary cutting forms is parallel to a width of the metal wire portions where the preliminary cutting forms are inserted. If the preliminary cutting forms have width parallel to the width of the metal wire portion, the preliminary cutting forms become part of a cutting form final layout. Cutting forms not having widths parallel to the width of the metal wire portions are removed. Cutting forms at different orientations are then inserted where the prior cutting forms were removed from and the process repeats until all portions of the metal wire have cutting forms inserted parallel to the current flow direction.

Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array is provided. The STT-MRAM array includes a STT-MRAM bit cell and an input net coupled to the STT-MRAM bit cell. The STT-MRAM array includes a pulse signal input pad and a buffer coupled between the pulse signal input pad and the input net. In an aspect, the input net is one of a bit line, a word line, and a source line.

Abstract: In a particular embodiment, a method is disclosed that includes detecting a first pitch between at least two lines (e.g. a power line and a ground line) of a first reference macro. The method also includes generating a virtual grid based on the first pitch and aligning at least a second macro to the virtual grid.