Patents Represented by Attorney, Agent or Law Firm Sam Talpalatsky
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Patent number: 8085581Abstract: A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell is provided. The STT-MRAM includes a rectangular bottom electrode (BE) plate, and a storage element on the rectangular bottom electrode (BE) plate. A difference between a width of the rectangular bottom electrode (BE) plate and a width of the storage element is equal to or greater than a predetermined minimum spacing requirement. A width of the bottom electrode (BE) plate is substantially equal to a width of an active layer or a width of a plurality of metal layers.Type: GrantFiled: August 28, 2008Date of Patent: December 27, 2011Assignee: QUALCOMM IncorporatedInventor: William Xia
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Patent number: 8081037Abstract: An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.Type: GrantFiled: June 11, 2008Date of Patent: December 20, 2011Assignee: QUALCOMM IncorporatedInventors: Jonghae Kim, Lew G. Chua-Eoan, Matthew Nowak
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Patent number: 8082401Abstract: Multi-ported memory systems (e.g., register files) employ self-timing for operational synchronization. Thus, rather than using a reference clock duty cycle for operational synchronization, as in conventional multi-ported register files, embodiments of the present disclosure employ self-timing for such operational synchronization. According to certain embodiments, self-timing is employed to synchronize all the internal events within the memory so that all the events are spaced in time for appropriate synchronization. For instance, the completion of one event leads to triggering another event, the completion of which leads to triggering another event, and so on. Thus, in one embodiment, the self-timing is achieved by referencing the operational events with the memory (or register file) to each other, rather than to a reference clock duty cycle.Type: GrantFiled: March 25, 2009Date of Patent: December 20, 2011Inventors: Hari Rao, Chang Ho Jung, Nan Chen, Sei Seung Yoon
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Patent number: 8063674Abstract: A multiple supply voltage device includes an input/output (I/O) network operative at a first supply voltage, a core network coupled to the I/O network and operative at a second supply voltage, and a power-on-control (POC) network coupled to the I/O network and the core network. The POC network is configured to transmit a POC signal to the I/O network and includes an adjustable current power up/down detector configured to detect a power state of the core network. The POC network also includes processing circuitry coupled to the adjustable current power up/down detector and configured to process the power state into the POC signal, and one or more feedback circuits. For reducing the leakage current while also improving the power-up/down detection speed, the feedback circuit(s) are coupled to the adjustable current power up/down detector and configured to provide feedback signals to adjust a current capacity of the adjustable current power up/down detector.Type: GrantFiled: February 4, 2009Date of Patent: November 22, 2011Assignee: QUALCOMM IncorporatedInventors: Chang Ki Kwon, Vivek Mohan
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Patent number: 8037385Abstract: A scan chain circuit is disclosed. The scan chain circuit includes a chain of serially coupled clocked circuits. In a first mode of operation, each of the clocked circuits toggles in response to a rising edge of a clock signal. In a second mode of operation, a first set of the clocked circuits in the chain of serially coupled clocked circuits toggle in response to the rising edge of the clock signal and a second set of the clocked circuits in the chain of serially coupled clocked circuits toggle in response to a falling edge of the clock signal.Type: GrantFiled: December 12, 2008Date of Patent: October 11, 2011Assignee: QUALCOMM IncorporatInventor: Triveni Rachapalli
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Patent number: 8030982Abstract: A clock gating cell that comprises a latch in communication with an input enable logic and an output logic circuit, wherein the latch includes a pull-up and/or a pull-down circuit at an input node of the output logic circuit and circuitry preventing premature charge or discharge of the output logic circuit input node by the pull-up and/or the pull-down circuit when the clock gating cell is enabled.Type: GrantFiled: October 30, 2008Date of Patent: October 4, 2011Assignee: QUALCOMM IncorporatedInventors: Animesh Datta, Martin Saint-Laurent, Varun Verma, Prayag B. Patel
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Patent number: 7979832Abstract: Methods and systems for designing process variation tolerant memory are disclosed. A memory circuit is divided into functional blocks. A statistical distribution is calculated for each of the functional blocks. Then, the distributions of each block are combined to verify a credibility of the circuit. The credibility is verified if the circuit meets a predetermined yield.Type: GrantFiled: October 17, 2007Date of Patent: July 12, 2011Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Sei Seung Yoon, Hyunwoo Nho
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Patent number: 7961502Abstract: Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit can be maintained even while power is removed from the electronic device.Type: GrantFiled: December 4, 2008Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventor: Lew Chua-Eoan
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Patent number: 7962681Abstract: A circuit device includes a first input to receive a reset control signal and a second input coupled to an output of a latch. The circuit device also includes a logic circuit adapted to conditionally reset the latch based on a state of the output in response to receiving the reset control signal.Type: GrantFiled: January 9, 2008Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Cheng Zhong, Zhiqin Chen
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Patent number: 7936590Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.Type: GrantFiled: December 8, 2008Date of Patent: May 3, 2011Assignee: QUALCOMM IncorporatedInventors: Dongkyu Park, Anosh B. Davierwalla, Cheng Zhong, Mohamed Hassan Soliman Abu-Rahma, Sei Seung Yoon
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Patent number: 7936205Abstract: In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.Type: GrantFiled: June 17, 2009Date of Patent: May 3, 2011Assignee: QUALCOMM IncorporatedInventors: Xiaohua Kong, Lew G. Chua-Eoan
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Patent number: 7936596Abstract: In a particular embodiment, a magnetic tunnel junction (MTJ) structure is disclosed that includes an MTJ cell having multiple sidewalls that extend substantially normal to a surface of a substrate. Each of the multiple sidewalls includes a free layer to carry a unique magnetic domain. Each of the unique magnetic domains is adapted to store a digital value.Type: GrantFiled: February 1, 2008Date of Patent: May 3, 2011Assignee: QUALCOMM IncorporatedInventor: Xia Li
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Patent number: 7928807Abstract: The present invention provides a frequency synthesizer for a wireless communication system. The synthesizer includes an oscillator that generates an electronic signal as well as frequency dividers, frequency selectors and mixers. The signal generated by the oscillator is sequentially divided by the frequency dividers to produce a first group of frequencies, and the selectors and mixers are then capable of mixing the first group of frequencies according to instructions from control bits to produce a second group of frequencies which constitute UWB band frequencies. In this manner, the synthesizer can generate all 14 UWB band frequencies or particular UWB band groups using a single oscillator. One of the frequencies generated by the dividers can also be used as the baseband clock signal without requiring an additional frequency source.Type: GrantFiled: September 16, 2005Date of Patent: April 19, 2011Assignee: QUALCOMM IncorporatedInventor: Chinmaya Mishra
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Patent number: 7929501Abstract: Methods and apparatus related to efficiently communicating information, such as base station identification information and/or timing information, via beacon signals are described. Base station identification information and/or timing information is communicated via beacon signals. A beacon coding scheme is utilized in which different base station sectors in the communications system are associated with different sub-sets of beacon tones, e.g., a sub-set of 4 beacon tones. Different beacon tone sub-sets have at most 1 tone in common. A base station sector transmitter transmits a sequence of beacon signals, in accordance with a predetermined beacon tone hopping pattern, in a recurring timing structure, each beacon signal including one of the tones from its associated beacon tone subset.Type: GrantFiled: September 7, 2007Date of Patent: April 19, 2011Assignee: QUALCOMM IncorporatedInventors: Alexander Leonidov, Thomas Richardson
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Patent number: 7929619Abstract: Methods and apparatus for allocating tones for communications in the strip-symbol periods in an OFDM system are described. In a strip-symbol, the signal is transmitted using the tones in a tone subset, which is selected from a predetermined set of tone subsets according to a fixed schedule sequence. Adjacent base stations and sectors use the same set of tone subsets but different schedule sequence to minimize the number of collisions between the tone subsets used in adjacent sectors and neighboring cells.Type: GrantFiled: July 14, 2006Date of Patent: April 19, 2011Assignee: QUALCOMM IncorporatedInventors: Junyi Li, Tom Richardson
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Patent number: 7929334Abstract: A method of measuring resistance of a magnetic tunnel junction (MTJ) of an MRAM memory cell includes applying a voltage of a selected level to a memory cell comprising an MTJ in series with a memory cell transistor in a conducting state. A current through the memory cell is determined. A variable voltage is applied to a replica cell not having an MTJ and comprising a replica cell transistor in a conducting state. A value of the variable voltage is determined, wherein a resulting current through the replica cell is substantially the same as the current through the memory cell. The MTJ resistance is computed by taking the difference of the memory cell voltage and the determined variable replica cell voltage and dividing the result by the determined memory cell current.Type: GrantFiled: January 29, 2009Date of Patent: April 19, 2011Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Sei Seung Yoon, Xiaochun Zhu, Mohamed Abu-Rahma
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Patent number: 7919794Abstract: A memory including a memory cell and method for producing the memory cell are disclosed. The memory includes a substrate in a first plane. A first metal connection extending in a second plane is provided. The second plane is substantially perpendicular to the first plane. A magnetic tunnel junction (MTJ) is provided having a first layer coupled to the metal connection such that the first layer of the MTJ is oriented along the second plane.Type: GrantFiled: January 8, 2008Date of Patent: April 5, 2011Assignee: QUALCOMM, IncorporatedInventors: Shiqun Gu, Seung H. Kang, Matt Nowak
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Patent number: 7903761Abstract: The present invention provides a method and apparatus for correcting direct current (DC) offsets in radio output signals. The invention comprises a radio processor and a baseband processor. During a calibration routine, the baseband processor measures DC offset produced by the radio processor, generates a corresponding DC offset correction value, and writes the correction value to a discrete memory in the radio processor via a serial processor interface. During a subsequent normal receive operation, the radio processor reads the DC offset correction value from memory and feeds it into a into a digital to analog converter to produce an analog signal that in turn is fed into a radio receive path to nullify undesired DC offset.Type: GrantFiled: March 31, 2006Date of Patent: March 8, 2011Assignee: QUALCOMM IncorporatedInventor: Brian C. Joseph
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Patent number: 7904770Abstract: A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.Type: GrantFiled: September 9, 2008Date of Patent: March 8, 2011Assignee: QUALCOMM IncorporatedInventor: Thomas R. Toms
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Patent number: 7889585Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.Type: GrantFiled: December 18, 2008Date of Patent: February 15, 2011Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon, Mehdi Hamidi Sani