Abstract: The present invention provides a method and system for detecting corrupted data of a plurality of hard disk drives (HDDs) in a data storage subsystem. In this system a predetermined number of fixed blocks within each of the HDDs emulate a track of a first track format. The predetermined number of fixed blocks provide a logical track. The logical track of one of the plurality of HDDs is generated by the others of the plurality of HDDs. The plurality of logical tracks forming a plurality of track groups. In a first aspect the method and system comprises assigning each of the plurality of logical tracks an address translation (ADT) number, comparing each of the ADT numbers of the plurality of logical tracks to an expected value until a mismatch occurs in a logical track, and determining if other logical tracks in a same track group have accurate ADT numbers. The first aspect further includes reconstructing the logical track if the other tracks within the same track group have accurate ADT numbers.

Abstract: A computer system with reboot capability includes a processing mechanism, the processing mechanism supporting an operating system. The system further includes a service processor coupled to the processing mechanism, the service processor determining whether a reboot operation is needed. In addition, the computer system includes a memory mechanism coupled to the processing mechanism and the service processor, the memory mechanism storing a plurality of platform policy parameters and an automatic restart policy of the operating system to support the reboot operation of the service processor.

Abstract: A memory is modified so that read and write data are transferred on both rising and falling edges of a timing signal, thereby essentially doubling the data transfer rate from memory. In one embodiment, a dual-edge extended data out (DE.sup.2 DO) memory includes modified and improved circuits and operating methods, as compared to a standard extended data out (EDO) memory, so that read and write data are transferred on both rising and falling edges of a timing signal. In a described embodiment, DE.sup.2 DO dynamic RAM (DRAM) reads and writes data on the rising and falling edges of a column address strobe (CAS) timing signal. By transferring data on both the rising and falling edges of the timing signal, the data transfer rate to and from the memory is effectively doubled.

Abstract: A method and system for identifying frequency and length of time of execution of serialization instructions in a pipeline of a processing system, the processing including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least PMCs, includes counting a number of instructions forcing serialization or logically requiring serialization of the pipeline during a predetermined sampling period. Further included are counting a number of additional cycles required to complete the instructions during the predetermined sampling period, and determining a loss of efficiency from the counted number of instructions and the counted number of additional cycles accumulated during the predetermined sampling period.

Abstract: A system and method for providing a flash memory is disclosed. The flash memory includes a plurality of memory cells. Each memory cell includes a source and a gate. The method and system include providing a plurality of word lines and a plurality of select devices. Each word line is coupled with the gate of each memory cell of a portion of the plurality of memory cells. Each word line provides a specific voltage to the portion of the plurality of memory cells during a read of a memory cell of the portion of the plurality of memory cells. The plurality of select devices correspond with the plurality of word lines. Each select device is coupled with the source of each memory cell of the portion of the plurality of memory cells coupled with the corresponding word line. Each select device couples the source of each memory cell of the portion of the plurality of memory cell with a specific potential during the read of the memory cell.

Abstract: A method, and system for supporting a plurality of textual manipulations and inputs in a computer system transparently to application programs running on the computer system, with the computer system including a text services manager, are described. A method aspect includes receiving inputs to the computer system, providing at least one text service event handler through the text services manager in response to the received inputs, and processing the received inputs with the at least one text service event handler to provide appropriate textual outputs from the at least one application program.

Abstract: A system and method for providing a wavelength division multiplexer is disclosed. In one aspect, the system and method include providing a housing for the wavelength division multiplexer. The housing includes a first port having a first aperture therein, a second port having a second aperture and a first plurality of apertures therein, and a third port having a third aperture and a second plurality of apertures therein. The second and third apertures are coupled to the first aperture. The first plurality of apertures are disposed symmetrically around the second aperture. The second plurality of apertures are disposed symmetrically around the third aperture. In another aspect, the method and system include providing a wavelength division multiplexer. The wavelength division multiplexer includes a first port including a first collimator, a second port coupled to the first port, and a third port coupled to the first port.

Abstract: A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers allocated to the count and link registers. The method and system comprises an architected count register and an architected link register that are each connected to a look-ahead register. Information in the architected count or link register is copied into the look-ahead register when a branch instruction is encountered that will alter the contents of the count or link registers. Information in the look-ahead register is saved in a shadow register when an unresolved branch is encountered, and restored by the shadow register if the outcome of the unresolved branch is mispredicted.

Abstract: A method for systematic generation of one or more image groups to relate a plurality of images as a single group includes providing an image command sequence. The image command sequence controls an image capture session comprising one of a plurality of capture types, and further includes a first command, the first command initiating the image capture session and formation of a first group, a plurality of parameters, the plurality of parameters characterizing the first group as one of at least two image capture group formats, and a second command, the second command ending the image capture session, wherein the image command sequence results in the single group of related images, and wherein the related plurality of images are identified through use of the single group. A system includes a digital image capture device, the digital image capture device capable of capturing and processing image data, and a central processing unit within the digital image capture device.

Abstract: A capacitor is provided for analog applications which can be fabricated with processes conventionally employed to fabricate digital circuitry and which has line spacing that is smaller than interlayer spacing. The capacitor of the present invention is based on intralayer capacitive coupling, rather than interlayer capacitive coupling which is conventionally employed in prior art capacitors. A capacitance can be achieved with the capacitor of the present invention that is higher than can be obtained with conventional capacitors occupying an area on the integrated circuit structure having similar size. Additionally, the capacitor of the present invention can be formed from upper metal layer such as metal-3, metal-4, and metal-5, and when the capacitor is formed from any of the upper metal layers the parasitic capacitance to ground is small.

Abstract: A system and method for providing a memory in a semiconductor is disclosed. In one aspect, the method and system include providing a source implant in the semiconductor, providing a first anneal of the source implant in an oxidizing agent, and providing a drain implant in the semiconductor after the first anneal. In another aspect, the method and system include providing a source implant and a drain implant in the semiconductor, providing a mask, and providing an anneal of the source implant, the drain implant, and the mask in an oxidizing agent. The mask exposes the source implant while limiting exposure of at least a portion of the drain implant.

Abstract: A system and method for reducing flicker in a display system using a flicker reduction circuit. The display includes a series of scan lines, each of which includes a set of pixels. The display is controlled by a video signal, which includes a series of video lines containing control variables that control the intensity of the pixels in the corresponding scan line. In one embodiment of the flicker reduction circuit, the flicker reduction circuit receives two of the video lines as input, and delays one of the one video lines using a memory, such that its control variables are synchronized in time with the other undelayed video line. The difference between the intensity of the synchronized pairs of control variables is determined, and the difference is fed into a look-up table. Based on the difference, the look-up table provides a control value that is then applied to one of the original synchronized control variables to provide a modified control variable that reduces flicker on the display screen.

Abstract: A system for determining the lighting conditions of objects illuminated by light sources. The system is adapted for use in a three-dimensional graphics system in which a scene is provided having one or more objects. Each object is made up of one or more polygons comprising one or more surfaces. Each surface is delimited by a plurality of vertices. One or more light sources are disposed within the scene. The inventive system determines lighting conditions such as color and intensity for each surface of each object taking into account ambient lighting conditions and each of the light sources in an accelerated manner relative to conventional approaches. In the illustrative embodiment, the inventive system first pre-computes a lighting condition for a vertex and provides a first value representative thereof. This value is stored to avoid the computational expense of re-computing same for each subsequent lighting condition evaluated for the vertex.

Abstract: A system and method for separating a component signal having a predetermined wavelength from a signal carried over a range of wavelengths is disclosed. The system comprises a first filter for transmitting light of the predetermined wavelength. The component signal is reflected rather than transmitted. The system further comprises a second filter for transmitting light of a second predetermined wavelength. The second filter is in the transmission direction from the first filter. Thus, the component signal is separated by transmission by the first filter and reflection from the second filter.

Abstract: Method and system aspects control access through a synchronization primitive to a peripheral device in a processing system. A processing system in accordance with the present invention includes at least one central processing unit (CPU), and at least one peripheral device coupled to the at least one CPU, where the at least one peripheral device includes a synchronization primitive for controlling acquisition by at least one thread of execution from the at least one CPU. In a system aspect for controlling access, the system includes a circuit for sending a first signal from a component of the processing system to a synchronization primitive within the peripheral device to determine a state of the synchronization primitive, and acquiring control of the peripheral device when the synchronization primitive is in a released state.

Abstract: A method and system for accelerating a user interface on a display of an image capture unit is disclosed. The image capture unit includes a plurality of image files for providing a plurality of images, the image capture unit further includes controls for allowing an image to be viewed on the display and for allowing navigation between the plurality of images. In a first aspect a method and system in accordance with the present invention comprises providing a low resolution image, medium resolution image and high resolution image within each image file and allowing the medium resolution image to be viewed on the display. In a second aspect a method for accelerating a user interface on a display of an image capture unit in accordance with the present invention includes a plurality of image files for providing a plurality of images, each image file includes a high resolution image therein.

Abstract: Method and system aspects for allowing control of data transfer from at least one website on the Internet by a server system hosting the website are presented.In a method aspect, the method includes establishing limits in the server system for allowable connection links to clients, comparing a current transfer session to allowable connection links, and controlling the current transfer session according to comparison results. The allowable connection links further include a maximum time allowed for the current transfer session, and an image data size limit.In a system aspect, a server system includes mechanisms for establishing limits for allowable connection links to clients, for comparing a current transfer session to the allowable connection links, and for controlling the current transfer session according to comparison results.

Abstract: The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

Abstract: The present invention provides an improved rendering system for walk-through applications. The method and system for a walk-through image rendering system in a data processing system provides a first image based on a geometry-based rendering approach in which a user's view position is changing; and also provides a second image based on an image-based representation of a scene in which the user's view position is not changing.

Abstract: A system for typographic glyph construction includes a graphics system, a glyph server coupled to the graphics system, and an operating system coupled to the glyph server. An apparatus for typographic glyph construction of input text in a graphics system running on a computer system and output on an output device of the computer system includes a line layout core unit, a glyph cache unit coupled to the line layout core unit, an open font architecture services unit coupled to the glyph cache unit, at least one scaler unit coupled to the open font architecture unit, a font object management unit coupled to the at least one font scaler, and an attribute group support unit supporting a data structure for communication among the units of the apparatus.