Patents Represented by Attorney Sawyer Law Group
  • Patent number: 7614146
    Abstract: The present invention provides a circuit board structure and a method of fabricating circuit board structure the same, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.
    Type: Grant
    Filed: October 4, 2007
    Date of Patent: November 10, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Shih-Ping Hsu
  • Patent number: 7613574
    Abstract: The present invention provides a system and method for automatically deriving unique surrogate response data from experiment results in which inherent data loss occurs in a sufficient number of the samples to disallow quantitative effects estimation at the experimenter's desired level of confidence for statistical significance. In part, the unique surrogate response data sets of the present invention have four primary characteristics including: each is numerically analyzable; each may be more readily or directly obtained in which inherent data loss occurs; each provides a response value for an experiment trial; and each provides information on the effect of the change made to the process or system that would have been obtainable if the experiment samples had had no inherent data loss.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: November 3, 2009
    Assignee: S-Matrix
    Inventor: Richard P. Verseput
  • Patent number: 7609210
    Abstract: In accordance with an embodiment, a phased array antenna system includes a printed wiring board formed in rhombic shape that accommodates requirements for low observability and a beam forming network located within the printed wiring board. The beam forming network is located over substantially the entire printed wiring board. The embodiment includes connectors located on the backside of the printed wiring board. The back side connectors allow the array architecture to expand to include more subarrays and therefore allowing for more beam forming elements in a full size array than conventional phased arrays.
    Type: Grant
    Filed: June 22, 2007
    Date of Patent: October 27, 2009
    Assignee: Boeing Company
    Inventors: Ming Chen, Robert L. Wightman, Dan R. Miller, Chris D. McKinley
  • Patent number: 7608907
    Abstract: An improved diode is disclosed. The diode comprises a Schottky diode and a LDMOS device coupled in series with the Schottky diode. In a preferred embodiment, a forward current from the Schottky diode is allowed to flow through the channel of a depletion mode LDMOS that allows gate control over Schottky forward current. Integrating the Schottky diode into the drain of the depletion mode LDMOS forms the device structure.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: October 27, 2009
    Assignee: Micrel, Inc.
    Inventor: Shekar Mallikarjunaswamy
  • Patent number: 7608929
    Abstract: An electrical connector structure of circuit board and a method for fabricating the same are proposed. A circuit board having a conductive layer is formed with a first resist layer and a second resist layer thereon, so as to form electrical connection pads and metal bumps on the electrical connection pads. The first and second resist layers are formed with openings therein at positions corresponding to the electrical connection pads and metal bumps, and the exposed conductive layer is removed. An adhesive layer is formed to cover the exposed surfaces of the electrical connection pads and the metal bumps. Then, the second resist layer, the first resist layer and the conductive layer covered by the first resist layer are removed. Later, an insulating protective layer is formed on a surface of the circuit board, and thinned to expose a portion of the adhesive layer, such that electrical connectors of the circuit board are fabricated.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: October 27, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Wen-Hung Hu
  • Patent number: 7608469
    Abstract: A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective.
    Type: Grant
    Filed: August 25, 2005
    Date of Patent: October 27, 2009
    Assignee: Kingston Technology Corporation
    Inventor: Wei Koh
  • Patent number: 7606685
    Abstract: A method, system and computer readable medium are disclosed. The method, system and computer readable medium comprises providing a mathematically linked multi-step process for simultaneously determining operating conditions of a system or process that will result in optimum performance in both mean performance requirements and system robustness requirements. In a method and system in accordance with the present embodiment, the steps can be applied to any data array that contains the two coordinated data elements defined previously (independent variables and response variables), and for which a response prediction model can be derived that relates the two elements. The steps are applied to each row of the data array, and result in a predicted Cp response data set. In the preferred embodiment the array is a statistically rigorous designed experiment from which mean performance prediction models can be derived for each response evaluated. The data are applied to each row of the data array.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: October 20, 2009
    Assignee: S-Matrix
    Inventors: Richard P. Verseput, George A. Cooney, Jr.
  • Patent number: 7606166
    Abstract: A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: October 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Claude Basso, Jean Louis Calvignac, Chih-jen Chang, Philippe Damon, Ronald Edward Fuhs, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli, Scott Michael Willenborg
  • Patent number: 7601563
    Abstract: A shape-molding structure of a memory card comprises a circuit substrate, at least one chip, and an encapsulant covering. The upper and lower surfaces of the circuit substrate have a circuit layer and a plurality of electric contacts, respectively. The chip is located on the upper surface of the circuit substrate and electrically connected with the circuit layer. The encapsulant covering is formed by using a mold to press encapsulant entering at least one encapsulant inlet provided on at least one side surface of the circuit substrate. The encapsulant covering encapsulates all the above components with only the electric contacts exposed. A trace mark of the encapsulant inlet remaining on the encapsulant covering is then cut to obtain a shape-molding structure of memory card with an smooth and intact outer appearance.
    Type: Grant
    Filed: January 18, 2007
    Date of Patent: October 13, 2009
    Assignee: Kingston Technology Corporation
    Inventors: Ben Wei Chen, Jin S. Wang, David Hong-Dien Chen
  • Patent number: 7597286
    Abstract: A mounting rail system for a cabin services system of an aircraft is disclosed. The mounting rail system comprises a mounting rail for providing power, and at least one circuit coupled to the mounting rail for allowing for operation of functionalities of a passenger services unit.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 6, 2009
    Assignee: Boeing Company
    Inventors: Kevin S. Callahan, Trevor M. Laib, Bret L. Lamoree, Donald B. Lee, Bradley J. Mitchell, William C. Sanford
  • Patent number: 7597572
    Abstract: Aspects of the present invention include a method and apparatus for an improved USB device having ESD protection. Uniquely including and positioning a discharge plane of a low resistance within a USB connection that is connectable with the ground of the USB connector, creates a discharge gap area where excess ESD charge may jump and discharge prior to the connection of paired USB devices having connectable connections.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 6, 2009
    Assignee: Lenovo Singapore Pte. Ltd
    Inventors: Cory A. Chapman, Albert V. Makley, Marc R. Pamley, Kenneth Seethaler
  • Patent number: 7594630
    Abstract: A mounting fixture for a computer peripheral is disclosed. The fixture comprises a mounting member adapted to be coupled to the peripheral; and a magnet coupled to the mounting member. The magnet couples the fixture to a housing. Accordingly, a mounting fixture is provided which can easily be adapted to a variety of peripheral devices to allow for their attachment to a computer or the like. By utilizing a magnet with a mounting member, a peripheral can easily and securely be mounted on the computer with minimal modification thereof.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: September 29, 2009
    Assignee: Apple Inc.
    Inventors: John P. Ternus, Eric Knopf, Sean Corbin, Daniele De Iuliis, Shin Nishibori
  • Patent number: 7593155
    Abstract: A system and method for the temporal and phase modulation of beams through a series of electronically controlled grating modulators, as acousto optic devices (AODs), is provided where incoming electromagnetic radiation may be advanced or retarded by introducing a time delay of the associated optical phase fronts and implementing a varying chirped wave on an AOD.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: September 22, 2009
    Assignee: Boeing Company
    Inventor: Paul Richard Herz
  • Patent number: 7589567
    Abstract: A circuit is provided that includes a current source, and a compensation circuit to generate a compensation current based on an output voltage of the current source. The circuit further includes a combiner to combine the compensation current with an output current of the current source to substantially cancel a channel-length modulation effect associated with the output current of the current source.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: September 15, 2009
    Assignee: Aquantia Corporation
    Inventor: Ramin Farjadrad
  • Patent number: 7590845
    Abstract: A method for a plurality of key cache managers for a plurality of localities to share cryptographic key storage resources of a security chip, includes: loading an application key into the key storage; and saving a restoration data for the application key by a key cache manager, where the restoration data can be used by the key cache manager to re-load the application key into the key storage if the application key is evicted from the key storage by another key cache manager. The method allows each of a plurality of key cache managers to recognize that its key had been removed from the security chip and to restore its key. The method also allows each key cache manager to evict or destroy any key currently loaded on the security chip without affecting the functionality of other localities.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: September 15, 2009
    Assignee: Lenovo Singapore Pte. Ltd.
    Inventors: Charles Douglas Ball, Ryan Charles Catherman, James Patrick Hoff, James Peter Ward
  • Patent number: 7590866
    Abstract: Super distribution of protected digital content is disclosed. According to one embodiment of the invention previously purchased encrypted digital content is received from a purchaser of the digital content. The purchaser of the previously purchased encrypted digital content is different from the recipient of the encrypted digital content. A secure transmission is established with an authorization authority for decrypting the content. A first decryption key for decrypting at least part of the previously purchased encrypted content as permitted by the authorization authority is received from the authorization authority. The at least part of the previously purchased encrypted content is decrypted as permitted by the authorization authority.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: September 15, 2009
    Assignee: International Business Machines Corporation
    Inventors: Marco M. Hurtado, James C. Mahlbacher, Richard L. Spagna
  • Patent number: 7586997
    Abstract: A communication system is provided that includes signal encoding in a multiple input multiple output system. The communication system includes wireless communication networks. The communication system includes methods of encoding and transmitting symbols in a rate-1 complex symbol per second per Hertz transmission system while achieving maximum diversity. The communication further includes methods of interleaving the complex symbols such that each interleaved symbol comprises information of at least two complex symbols where the complex symbols obtain values from a rotated constellation.
    Type: Grant
    Filed: August 16, 2005
    Date of Patent: September 8, 2009
    Assignee: Beceem Communications Inc.
    Inventors: Shashidhar Vummintala, Arogyaswami Paulraj, Erik D. Lindskog, Balaji S. Rajan, Djordje Tujkovic
  • Patent number: 7587495
    Abstract: A system for automatic configuration of computers on a network is disclosed. In a first aspect a storage area network is disclosed. The network comprises at least one controller; and a plurality of clients coupled to the at least one controller. The network includes a storage device coupled to the at least one controller and the plurality of clients. The controller upon attachment to the network registers itself and notifies the plurality of clients. The plurality of clients then interrogates the controller. Each of the plurality of clients updates its configuration based upon the interrogation. In a second aspect, a method for configuration of computers in a network is disclosed. The method comprises registering at least one controller upon attachment to the network and notifying a plurality of clients by the at least one controller The method includes interrogating the at least one controller by each of the plurality of clients. The plurality of clients are updated based upon the interrogation.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: September 8, 2009
    Assignee: APPLE Inc
    Inventors: Jean François Albouze, Michael R. Margolis
  • Patent number: 7586936
    Abstract: An Ethernet adapter is disclosed. The Ethernet adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a demultiplexing mechanism to allow for partitioning of the processor. A Host Ethernet Adapter (HEA) is an integrated Ethernet adapter providing a new approach to Ethernet and TCP acceleration. A set of TCP/IP acceleration features have been introduced in a toolkit approach: Servers TCP/IP stacks use these accelerators when and as required. The interface between the server and the network interface controller has been streamlined by bypassing the PCI bus. The HEA supports network virtualization. The HEA can be shared by multiple OSs providing the essential isolation and protection without affecting its performance.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: September 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Claude Basso, Jean Louis Calvignac, Chih-Jen Chang, Philippe Damon, Ronald Edward Fuhs, Satya Prakash Sharma, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli, Scott Michael Willenborg
  • Patent number: 7587383
    Abstract: A method, computer readable medium, and system for optimizing a query in a relational database processing system is disclosed. The present invention relates to a query rewrite optimization method for eliminating a redundant join and equivalent subquery in an SQL query before generation and selection of the optimal query execution plan. The method of the present invention includes evaluating the query to identify a join predicate joining a sub-expression of the query to itself, and determining whether a row set producible from a first set of references of the query to the sub-expression is subsumed by a row set producible from a second set of references of the query to the sub-expression. Based on such evaluation and determination, the query may be reformed to eliminate the join predicate and the second quantifier. A further determination of the removability of the second quantifier may be required such as by evaluating a cardinality constraint when query output cardinality is material.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: September 8, 2009
    Assignee: International Business Machines Corporation
    Inventors: Fred Koo, Ting Y. Leung