Abstract: A FLASH memory controller is disclosed. The controller comprises a microcontroller. The microcontroller including firmware for providing different mappings for different types of FLASH memory chips. The controller also includes FLASH control logic for communicating with the microcontroller and adapted to communicate via a FLASH data bus to at least one FLASH memory chip. The FLASH control logic including mapping logic for configuring the FLASH data bus based upon the type of FLASH memory chip coupled thereto. A method and system in accordance with the present invention provides the following advantages: Configurable data bus on the FLASH memory controller through software to simplify routing complexity. Configurable chip select and control bus for flexibility of FLASH memory placement. Elimination of external resistor network for layout simplicity. A scalable architecture for higher data bus bandwidth support. Auto-detection of FLASH memory type and capacity configuration.

Abstract: A system and computer readable medium for processing a request to retrieve data from a database is disclosed. The system and computer readable medium of the present invention comprises receiving the request which comprises a function that processes at least one data item specified in the request, retrieving the at least one data item from a database, and invoking the function. When the function is invoked, at least one parameter comprising information related to the at least one data item is passed to the function. Thus, a function can be written independently of the data which they are called to process.

Abstract: The retrieval of distinct tuples in a relational database management system. In response to a request from a consumer process for distinct tuples in a relational database table matching a defined criteria, a distinct operator component sequentially requests tuples from a source component. The source component access the database table and returns a tuple in the sequence to the distinct operator component. The distinct operator component passes each tuple in the sequence to an auxiliary logger. The auxiliary component receives a tuples from the distinct component and determines if it is distinct from other previously received tuples in the sequence to verify its uniqueness to the distinct operator. Tuples that are verified as unique by the auxiliary logger are returned to the consumer process by the distinct operator upon verification.

Abstract: An apparatus for use within an electrical devices is disclosed. The apparatus comprises a casing having an upper body and a lower body, the casing including a tab disposed on a surface thereof and an adjustable base having a plurality of tab cavities adjacent to the tab. The tab engagingly couples to one of the plurality of tab cavities to secure the adjustable base. The apparatus also includes a connector system coupled to the adjustable base.

Abstract: The present invention relates to a method and system for displaying a video signal in dependence on a user interaction. The system comprises a display for receiving the video signal, at least one transmitter for transmitting location signals, and at least three transceivers for receiving the location signals from the transmitter and for transmitting modified location signals. The geometric locations of the at least three transceivers are known to a computing device. The computing device is then able to derive a transmit location of the location signals based on the received modified location signals, wherein the computing device is adapted to modify the content of the video signal in response to the derived transmit location in dependence on the user interaction.

Abstract: A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associated with a programmable transmitter that is in communication with the device. The biased bits correspond to the variable nodes of the dominant trapping set. The method further includes transmitting random data from the programmable transmitter to the device, in which the random data includes one or more of the biased bits; measuring a number of error events corresponding to biased bits received by the device that cannot be decoded; and determining a true bit error rate of the device based on the measured number of error events.

Abstract: Virtual solution architecture for computer data systems. In one aspect, providing an architecture for a computer data system includes creating a virtual solution architecture that includes a plurality of building blocks, each building block characterized by balanced operation, and mapping the virtual solution architecture to a physical solution architecture for the computer data system. Another aspect includes providing at least one balanced configuration unit (BCU) in a computer data system, the BCU including at least one balanced partition unit (BPU) that includes computer resources to provide balanced operation for the BPU.

Abstract: A method for committing transactions in a distributed system are provided. The method provides for receiving a request from a client to commit a transaction at a coordinator node in the distributed system, tracking a tail log sequence number for every other node in the distributed system, determining a max log sequence number associated with the transaction for each participant node in the distributed system, and committing the transaction at the coordinator node when the tail log sequence number for each participant node is greater than or equal to the max log sequence number associated with the transaction at the respective participant node.

Abstract: A package substrate and a method for fabricating the same are provided according to the present invention. The package substrate includes: a substrate body with a die attaching side and a ball implanting side lying opposite each other, having a plurality of wire bonding pads and a plurality of solder ball pads respectively, and having a first insulating passivation layer and a second insulating passivation layer respectively, wherein a plurality of first apertures and a plurality of second apertures are formed in the first insulating passivation layer and the second insulation passivation layer respectively to corresponding expose the wire bonding pads and the solder ball pads; a chemical plating metal layer formed on the wire bonding pads and solder ball pads respectively; and a wire bonding metal layer formed on a surface of the chemical plating metal layer of the wire bonding metal layer.

Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.

Abstract: An electrically connecting terminal structure of a circuit board and a manufacturing method thereof are disclosed.

Abstract: An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth.

Abstract: A method for generating an execution plan for updating and retrieving data from a database in a single process includes: receiving a statement by a server to update a database with a first set of data and to retrieve a second set of data from the database; building a first execution plan to update the database with the first set of data; building a second execution plan to retrieve the second set of data from the database; and building a single execution plan including a combination of the first and second execution plans. The single execution plan allows for the updating and retrieval of data with a single crossing of an interface between a client and the database. By performing both functions in this manner, the efficiency of performing such tasks on the database is significantly increased.

Abstract: Method and system for designing integrated circuits for yield are described. Integrated circuits are designed for yield by finding worst yield corners based on design, statistical, and environmental variables and optimizing the design in light of the worst yield corners found.

Abstract: This invention relates to apparatus and method to fast determine focus parameters in one pre-scan during an e-beam inspection practice. More specifically, embodiments of the present invention provide an apparatus and method that provide accurate focus tuning after primary focusing has been done.

Abstract: An input buffer circuit. In one embodiment, the input buffer circuit includes a first transistor operable to receive a first input signal, a second transistor operable to receive a second input signal, and a first mechanism coupled to the first transistor and to the second transistor. The first mechanism is operable to control the first and second transistors such that the first and second transistors can receive either single-ended input signals or differential input signals. According to the embodiments disclosed herein, the input buffer combines single-ended input and differential input functionalities without compromising performance.

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract: A conductive bump structure of a circuit board and a method for forming the same are proposed. A conductive layer is formed on an insulating layer on the surface of the circuit board. A first resist layer is formed on the conductive layer and a plurality of first openings is formed in the first resist layer to expose the conductive layer. Then, a patterned trace layer is electroplated in the first openings and a second resist layer is covered on the circuit board with the patterned trace layer. Second openings are formed in the second resist layer to expose part of the trace layer to be used as electrical connecting pads. Thereafter, metal bumps are electroplated in the second openings and the surface of the circuit board is covered with a solder mask. A thinning process is applied to the solder mask to expose the top surface of the metal bumps. Afterwards, an adhesive layer is formed on the surface of the metal bumps exposing out of the solder mask.

Abstract: Systems and methods are provided for improving a channel estimate in a signal communication system. The systems and methods improve the channel estimation quality and/or the delay spread of the channels that can be estimated. The combining of symbols operates to increase the density of pilots that are processed to provide the channel estimate.

Abstract: A dual offset reflector system is disclosed. The system comprises a main reflector, a subreflector, a first gimbal mechanism for positioning of the subreflector. The system includes at least two feeds for receiving beams from the main reflector and the subreflector. One of the feds is at a focal point of the system and the other beam is displaced from the focal point. Accordingly, a simple solution to restore antenna gain reduction and avoid beam distortion due to the scan loss for a reflector system is provided that utilizes multiple feeds at different frequencies and polarizations. By placing the feeds at focal point trajectory of the subreflector whose positioning is controlled by a gimbal mechanism, a system is provided that minimizes distant and scan loss in a dual reflector system. The gimbal mechanism positions the subreflector so that a desired feed is in the focal point of the subreflector.