Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

Abstract: A semiconductor power device package having a lead frame-based integrated inductor is disclosed. The semiconductor power device package includes a lead frame having a plurality of leads, a inductor core attached to the lead frame such that a plurality of lead ends are exposed through a window formed in the inductor core, a plurality of bonding wires, ones of the plurality of bonding wires coupling each of the plurality of lead ends to adjacent leads about the inductor core to form the inductor, and a power integrated circuit coupled to the inductor. In alternative embodiments, a top lead frame couples each of the plurality of lead ends to adjacent leads about the inductor core by means of a connection chip.

Abstract: A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.

Abstract: A multilayer inductor is disclosed. The multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element. The spiral inductor element is coupled to the first inductor electrode by means of a through hole formed in the bottom magnetic layer and to the second inductor electrode by means of power conductive traces formed on side surfaces of the multilayer inductor.

Abstract: A wafer level chip scale package and method of laser marking the same are disclosed. The method includes forming a plurality of semiconductor devices on a frontside surface of a wafer, metallizing device contacts on the frontside surface of the wafer, grinding the backside surface of the wafer, silicon etching the backside surface of the wafer, laser marking the backside surface of the wafer following the silicon etch step, oxide etching the backside surface of the wafer following the laser marking step, depositing a metal layer on the backside surface of the wafer following the oxide etch step, and dicing the wafer into wafer level chip scale packages. A wafer level chip scale package includes a mark formed on a backside surface thereof, the mark comprising a plurality of trenches formed in a silicon backside surface and corresponding indentations formed in an overlaying back metal layer.

Abstract: A method of fabricating a semiconductor device employing electroless plating including wafer backside protection during wet processing is disclosed. The method includes the steps of laminating a wafer back side and a frame with a protective tape, applying a protective coating to a peripheral portion of the wafer and an adjoining exposed area of the protective tape, the protective coating, protective tape, and wafer forming a protected wafer assembly, curing the frame-supported protective coating, cutting the protected wafer assembly from the protective tape surrounding the protective coating, wet processing the protected wafer assembly, laminating the protected wafer assembly with a second tape, dicing the wafer, and picking up the die from the protective tape.

Abstract: A power device includes a discrete inductor having contacts formed on a first surface of the discrete inductor and at least one semiconductor component mounted on the first surface of the discrete inductor and coupled to the contacts. The discrete inductor further includes contacts formed on a second surface opposite the first surface and routing connections connecting the first surface contacts to corresponding second surface contacts. The semiconductor components may be flip chip mounted onto the discrete inductor contacts or wire bonded thereto.

Abstract: A dual flat non-leaded semiconductor package is disclosed. A method of making a dual flat non-leaded semiconductor package includes forming a leadframe having a die bonding area with an integral drain lead, a gate lead bonding area and a source lead bonding area, the gate lead bonding area and a source lead bonding area being of increased area; bonding a die to the die bonding area; coupling a die source bonding area to the source lead bonding area; coupling a die gate bonding area to the gate lead bonding area; and partially encapsulating the die, the drain lead, the gate lead and the source lead to form the dual flat non-leaded semiconductor package.

Abstract: A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.

Abstract: A high current semiconductor power SOIC package is disclosed. The package includes a relatively thick lead frame formed of a single gauge material having a thickness greater than 8 mils, the lead frame having a plurality of leads and a first lead frame pad, the first lead frame pad including a die soldered thereto; a pair of lead bonding areas being disposed in a same plane of a top surface of the die; large diameter bonding wires connecting the die to the plurality of leads, the bonding wires being aluminum; and a resin body encapsulating the die, bonding wires and at least a portion of the lead frame.

Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.

Abstract: A direct gold/silicon eutectic die bonding method is disclosed. The method includes the steps of gold plating a die bonding pad, grinding a wafer to a desired thickness, dicing the wafer after the grinding step, picking a die, and attaching the die to the die bonding pad at a temperature above the gold/silicon eutectic temperature. For thinner wafers, a dicing before grinding process is employed.

Abstract: A system for reclaiming residual unspent automotive fluid having a fluid receiver which seats open containers of the automotive fluid in an inverted orientation to allow influences of gravity to self-drain the open containers. The fluid receiver accumulates the residual unspent automotive fluid into classifying compartments. Each compartment can be individually pumped or drained of the accumulated and stored residual automotive fluid.

Abstract: An off-circuit tap changer device which includes a spring-biased moving contact that is operable to independent flex and roll. The moving contact includes one or more rings which are independently spring biased to a moving contact support. The device also includes a single rod with locking elongated ribs to mate with a sleeve of the moving contact support. The circulating circuit includes X stationary contacts. The resiliency via the spring-biasing and the rolling of the ring minimizes, if not prevents, surface wearing of the moving contacts.

Abstract: A high throughput combinatorial screening method and apparatus for the evaluation of electrochemical materials using a single voltage source (2) is disclosed wherein temperature changes arising from the application of an electrical load to a cell array (1) are used to evaluate the relative electrochemical efficiency of the materials comprising the array. The apparatus may include an array of electrochemical cells (1) that are connected to each other in parallel or in series, an electronic load (2) for applying a voltage or current to the electrochemical cells (1), and a device (3), external to the cells, for monitoring the relative temperature of each cell when the load is applied.