Patents Represented by Attorney Scott Hewett
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Patent number: 8350365Abstract: A hard implantation mask layer is formed on a semiconductor wafer. An etch mask layer is formed on the hard implantation mask layer and patterned. The hard implantation mask layer is etched to form a well implantation pattern and ions are implanted into the semiconductor wafer to form wells in the semiconductor wafer, in areas where the semiconductor wafer is not covered by the well implantation mask.Type: GrantFiled: January 13, 2011Date of Patent: January 8, 2013Assignee: Xilinx, Inc.Inventors: Yun Wu, Hong-Tsz Pan, Qi Lin, Bang-Thu Nguyen
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Patent number: 8351248Abstract: A memory cell in an integrated circuit has a first PMOS transistor formed in N-type semiconductor material and a first NMOS transistor formed in P-type semiconductor material. A well bias line coupled to the N-type semiconductor material or to the P-type semiconductor material provides a well bias voltage not equal to the PMOS bias voltage or to the NMOS bias voltage to reverse body-bias the PMOS transistor or to forward body-bias the NMOS transistor.Type: GrantFiled: November 23, 2009Date of Patent: January 8, 2013Assignee: Xilinx, Inc.Inventor: Michael J. Hart
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Patent number: 8350253Abstract: An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.Type: GrantFiled: January 29, 2010Date of Patent: January 8, 2013Assignee: Xilinx, Inc.Inventors: Bei Zhu, Hong-Tze Pan, Bang-Thu Nguyen, Qi Lin, Zhiyuan Wu, Ping-Chin Yeh, Jae-Gyung Ahn, Yun Wu
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Patent number: 8295099Abstract: A data value is read from one port of a dual-port memory cell during a clock cycle. A WRITE assist pulse having a delay from an end-of-read signal is generated. The delay and duration of the WRITE assist pulse are optionally user-selectable. A high voltage (e.g., Vdd) is coupled to the bitlines (e.g., BL-A, BLc-A) of the first port during the WRITE assist pulse, and a low voltage value (e.g., zero) is written to the memory cell through the second port (e.g., BL-B, BLc-B) during the clock cycle.Type: GrantFiled: May 28, 2010Date of Patent: October 23, 2012Assignee: Xilinx, Inc.Inventors: Santosh Yachareni, Subodh Kumar, Hsiao Chen
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Patent number: 8265917Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.Type: GrantFiled: February 25, 2008Date of Patent: September 11, 2012Assignee: Xilinx, Inc.Inventors: Jingzhao Ou, Shay Ping Seng
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Patent number: 8207592Abstract: A capacitor in an integrated circuit (“IC”) has a first plurality of conductive crosses formed in a layer of the IC electrically connected to and forming a portion of a first node of the capacitor and a second plurality of conductive crosses formed in the metal layer of the IC. The conductive crosses in the second plurality of conductive crosses are electrically connected to and form a portion of a second node of the capacitor and capacitively couple to the first node.Type: GrantFiled: November 21, 2008Date of Patent: June 26, 2012Assignee: Xilinx, Inc.Inventor: Patrick J. Quinn
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Patent number: 8179159Abstract: A method of configuring a stacked integrated circuit (“IC”) having a first IC die with configurable logic and a second IC die electrically coupled to the first IC die through an array of inter-chip contacts includes: providing a frame having frame data and a frame address in a frame header to the first IC die; storing the frame data in a frame data register of the first IC die; processing the frame header to determine whether a frame destination is in the first IC die or the second IC die; in response to determining that the frame destination is in the second IC die, providing the frame address to the second IC die through an inter-chip frame address bus including a first plurality of the array of inter-chip contacts; and writing the frame data from the frame data register of the first IC die to the frame destination through an inter-chip frame data bus including a second plurality of the array of inter-chip contacts.Type: GrantFiled: May 26, 2011Date of Patent: May 15, 2012Assignee: Xilinx, Inc.Inventors: Stephen M. Trimberger, Arifur Rahman
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Patent number: 8146028Abstract: An integrated circuit (“IC”) (100) is configured to have two instantiations of a user design (103, 105). Register values from the first instantiation (RA1, RA2, RA3, RA4) are compared (102) to corresponding registers of the second instantiation (RB1, RB2, RB3, RB4). If a register pair does not match, the user designs are halted, re-loaded, and re-started.Type: GrantFiled: November 19, 2008Date of Patent: March 27, 2012Assignee: Xilinx, Inc.Inventor: Austin H. Lesea
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Patent number: 8143532Abstract: A through hole is formed in a circuit board that has fibers dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating over the sputtered copper layer.Type: GrantFiled: February 5, 2009Date of Patent: March 27, 2012Assignee: Xilinx, Inc.Inventor: Leilei Zhang
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Patent number: 8134813Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.Type: GrantFiled: January 29, 2009Date of Patent: March 13, 2012Assignee: Xilinx, Inc.Inventors: James Karp, Richard C. Li, Fu-Hing Ho, Mohammed Fakhruddin
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Patent number: 8121240Abstract: Phase shift is added between a uttering clock signal and a data bit stream clocked by the clock signal. The phase shift is adjusted until half the data bits are captured (counted) over a measurement period. Adding this amount of phase shift between the clock and data signals centers the average clock edge placement. In a particular embodiment, counters, each having N bits where N is an integer, are used to count clock pulses and data bits. When one counter is full and the most-significant bit on the other counter goes high, the phase shift between the data and clock signal places the average clock edge at the data bit edge.Type: GrantFiled: November 16, 2004Date of Patent: February 21, 2012Assignee: Xilinx, Inc.Inventor: Ajay Dalvi
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Patent number: 8122177Abstract: An integrated circuit (“IC”) includes a peripheral component interconnect express (“PCIe”) root complex having a central processing unit (“CPU”), a memory controller configured to control a main memory of a PCIe system, and a PCIe port coupled to a PCIe endpoint device through a PCIe switch. The PCIe endpoint device is configured to initiate data transfer between the main memory and the PCIe endpoint device.Type: GrantFiled: May 19, 2009Date of Patent: February 21, 2012Assignee: Xilinx, Inc.Inventor: Kiran S. Puranik
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Patent number: 8120430Abstract: A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.Type: GrantFiled: January 15, 2009Date of Patent: February 21, 2012Assignee: Xilinx, Inc.Inventor: Narasimhan Vasudevan
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Patent number: 8121826Abstract: A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the system. A text entry pane on the display device shows a textual definition of the connection. An optional status pane shows a textual log of user-performed actions relating to construction of the system.Type: GrantFiled: July 17, 2009Date of Patent: February 21, 2012Assignee: Xilinx, Inc.Inventors: Christopher E. Neely, Gordon J. Brebner, Jack S. Lo
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Patent number: 8082535Abstract: A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.Type: GrantFiled: February 3, 2009Date of Patent: December 20, 2011Assignee: Xilinx, Inc.Inventors: Ian L. McEwen, Teymour M. Mansour, Andrew G. Anderson, Reto Stamm
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Patent number: 8030954Abstract: Operation of an internal voltage supply level (Vgg) of an IC is characterized over operating temperature or at a selected temperature to determine a temperature-equivalent internal voltage level. The internal voltage supply of the IC is set to the temperature-equivalent level, and the IC is tested at room temperature to screen for low-temperature defects or high-temperature defects.Type: GrantFiled: January 14, 2009Date of Patent: October 4, 2011Assignee: Xilinx, Inc.Inventors: Srinivasa R. Parthasarathy, Lee Ni Chung, Jian Jun Shi, Randy J. Simmons
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Patent number: 8019019Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.Type: GrantFiled: September 1, 2009Date of Patent: September 13, 2011Assignee: Xilinx, Inc.Inventors: David E. Tetzlaff, Michael J. Gaboury
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Patent number: 8014184Abstract: A memory cell has a data value storage circuit and a data address circuit that includes a first address transistor formed in a first address transistor well and a second address transistor formed in a second address transistor well. The first address transistor is coupled between a data node and the second address transistor, and the second address transistor is coupled between the first address transistor and the data value storage circuit. The first address transistor well is coupled to an intermediate node between the first address transistor and the second address transistor, and the second address transistor well is coupled to a ground terminal.Type: GrantFiled: September 14, 2009Date of Patent: September 6, 2011Assignee: Xilinx, Inc.Inventor: Austin H. Lesea
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Patent number: 8000519Abstract: A method of evaluating an inline inspection recipe compares the capture rate of metal pattern defects in bounding boxes arising from failed electrical test vectors to the capture rate after the bounding box is shifted. A difference between the first and second capture rates indicates whether the inline inspection recipe is valid for capturing killer defects, or if the inline inspection recipe needs to be adjusted. In a particular example, the electrical test vectors are directed at a selected patterned metal layer of an FPGA (M6), and the metal pattern defect data for the selected patterned metal layer is mapped to the bounding box determined by the electrical test vector.Type: GrantFiled: April 4, 2007Date of Patent: August 16, 2011Assignee: Xilinx, Inc.Inventors: Yongjun Zheng, David Mark, Joe W. Zhao, Felino Encarnacion Pagaduan
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Patent number: 7994609Abstract: A capacitor in an integrated circuit (“IC”) includes a core capacitor portion having first conductive elements electrically connected to and forming a part of a first node of the capacitor formed in a first layer and second conductive elements electrically connected to and forming a part of a second node of the capacitor formed in the first layer. The first and second conductive elements alternate in the first conductive layer. Third conductive elements electrically connected to and forming a part of the first node are formed in a second layer adjacent to the first layer. The capacitor also includes a shield capacitor portion having fourth conductive elements formed in at least first, second, third, and fourth layers. The shield capacitor portion is electrically connected to and forms a part of the second node of the capacitor and surrounds the first and third conductive elements.Type: GrantFiled: November 21, 2008Date of Patent: August 9, 2011Assignee: Xilinx, Inc.Inventor: Patrick J. Quinn