Abstract: A memory cell with a logic bit has a first one-time-programmable (“OTP”) memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

Abstract: An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.

Abstract: A packaged integrated circuit (“IC”) includes a substrate, an IC die, and a molded plastic lid. A test point standoff is electrically connected to the IC die and extends away from the surface of the package substrate through the molded plastic lid toward the top surface of the molded plastic lid. The top of the test point standoff is below the top surface of the molded plastic lid.

Abstract: A reconfigurable module in a programmable logic device (“PLD”), such as a field-programmable gate array (“FPGA”), is reset after reconfiguration by an internal reset signal. The internal reset signal allows other modules in the PLD to remain active while the reconfigurable module is reconfigured and reset. The internal reset signal is generated by a reset manager circuit that optionally resides within the reconfigurable module.

Abstract: A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

Abstract: A field-effect transistor (“FET”) or similar device has a fully silicided (“FUSI”) gate electrode. The gate electrode has a gate interface silicide portion between the gate dielectric and a bulk gate silicide portion. The gate interface silicide is formed by depositing a gate electrode interface layer having silicide retardation species underneath the metal/silicon layers used to form the gate silicide. The gate electrode interface layer retards silicide formation at the gate dielectric/gate electrode interface when the bulk gate silicide is formed, and the gate interface silicide is then formed at a higher temperature or longer heat cycle time.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. An ohmic contact layer is formed in the recesses, and a stressed silicon-nitride layer is formed over the ohmic contact layer. The recesses allow the stressed silicon nitride layer to provide strain in the plane of the channel region. In a particular embodiment, a tensile silicon nitride layer is formed over recesses of an NMOS transistor in a CMOS cell, and a compressive silicon nitride layer is formed over recesses of a PMOS transistor in the CMOS cell. In a particular embodiment the stressed silicon nitride layer(s) is a chemical etch stop layer.

Abstract: A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Abstract: A charge pump circuit has a charge pump section and a replica charge pump section. The replica charge pump section produces a replica voltage at which the UP current will match the DOWN current. A comparator compares the replica voltage to the output voltage, and adjusts the bias to the charge pump section and replica charge pump section so that the voltage level produced by the replica charge pump section matches the output voltage.

Abstract: A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of the package substrate and against the sloped sidewall of the lid. The molding compound securely attaches the lid to the package substrate, providing improved reliability to the lid-substrate joint. The lightweight lid also increases standoff when a solder ball-grid array is used to connect the packaged IC to a printed wiring board, improving the reliability of the ball-grid array connections.

Abstract: An integrated circuit has an optical waveguide configured to carry a plurality of optical channels, which in a particular embodiment are optical clock signals generated by an optical clock generator. The integrated circuit includes an optical crossbar having a first output, a second output, a first optical ring resonator, and a second optical ring resonator. In a further embodiment, the optical crossbar is an optical crossbar switch and an output path in the optical crossbar switch includes another tunable optical ring resonator and an intermediate waveguide, which allows isolating the output from any optical channel on the on-chip optical waveguide by tuning the first ring resonator to a first wavelength, and tuning the other ring resonator to another wavelength.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Abstract: A first-in, first-out (“FIFO”) memory system embedded in a programmable logic device has an embedded FIFO memory array coupled to an output register. If the embedded FIFO memory is empty, the first word written to the FIFO memory system is pre-fetched to the output register. A first-word detection circuit asserts a DATA VALID signal if the first word is available to be read from the output register when READ ENABLE is asserted. In an alternative embodiment, the first word is pre-fetched to the output of the output register and is available to be read before READ ENABLE is asserted.

Abstract: The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

Abstract: A code is generated for a programmable logic device (“PLD”) having a plurality of regions including at least one defective region. The code indicates a defective region or regions of the PLD. A user enters the code before running placement and routing. A guide file associated with the code blocks out the defective region(s) of the PLD during placement and routing.

Abstract: A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is formed from a portion of the first stress layer overlying a second channel. A second stress layer providing a second stress type overlies the first modified stress layer and a second modified stress layer is formed from a portion of the second stress layer overlying the first stress layer.

Abstract: In an embodiment of the present invention, an integrated circuit (“IC”), such as a field-programmable gate array (“FPGA”) or a complex programmable logic device (“CPLD”), has a global clock buffer coupled to a first regional clock buffer through a first global clock spine. A first flip-flop is close to a first end of a first regional clock spine, and is coupled to a circuit block, such as a configurable logic block. The circuit block is coupled to the global clock buffer through a first routing portion and a second routing portion couples the first flip-flop to the circuit block so as to form a first clock ring allowing measurement of a first clock ring delay. In further embodiments, additional clock rings are configured in the IC, allowing measurements of additional clock ring delays. In suitably symmetric devices, skew along the regional clock spine is calculated from the clock ring delays.