Abstract: E-fuses in an E-fuse memory array are programmed by applying a first programming pulse to a plurality of E-fuses to program the plurality of E-fuses to a first state; and then applying a second programming pulse to at least a selected E-fuse in the plurality of E-fuses to program the selected E-fuse to a second state.

Abstract: An integrated circuit includes a pass gate having an input and an output. An NMOS pass transistor is connected between the input and the output. The drain of the NMOS pass transistor is connected to the input and the source of the NMOS pass transistor is connected to a node between the source of the NMOS transistor and the output of the pass gate. A current clamp is connected between the node and a current sink so as to conduct current to the current sink when the node reaches a threshold value.

Abstract: An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.

Abstract: A metal lid for packaging semiconductor chips is stamped to form a sloped sidewall with a set-back from the edge of a package substrate. After the metal lid is placed over the semiconductor chip, molding compound is formed around portions of the exposed perimeter of the package substrate and against the sloped sidewall of the lid. The molding compound securely attaches the lid to the package substrate, providing improved reliability to the lid-substrate joint. The lightweight lid also increases standoff when a solder ball-grid array is used to connect the packaged IC to a printed wiring board, improving the reliability of the ball-grid array connections.

Abstract: An IC uses a tunable interconnect driver between a data source and a data destination to selectively slow down (“de-tune”) data signals. Data sent along relatively short paths are de-tuned to reduce power supply noise during synchronous switching events. In some embodiments, the tunable interconnect driver delays data transmission relative to an un-delayed signal path, in other embodiments, the slew rate of the tunable interconnect driver is selectively reduced.

Abstract: A memory has first and second storage cells, each with a floating node, that store complementary data values. Interlaced inverters quickly sense a voltage difference between the storage cells and provide a data value output when the memory is read. Each floating node includes a tunneling gate of a tunneling transistor, a gate of a bitline transistor, and a plate of a coupling capacitor.

Abstract: An integrated circuit system (120) includes a memory array (122) storing a configuration data set to configure an integrated circuit. The integrated circuit (121) includes a configuration memory (128) and a configuration controller state machine (126). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array (122) and to compare the read-check signature with a standard signature stored in the integrated circuit (121). If the read-check signature passes the comparison, the configuration controller state machine (126) loads the configuration data set from the memory array to the configuration memory (128) of the integrated circuit.

Abstract: Fluid-based dielectric material is used to backfill multiple patterned metal layers of an IC on a wafer. The patterned metal layers are fabricated using conventional CMOS techniques, and are IMD layers in particular embodiments. The dielectric material(s) are etched out of the IC to form a metal network, and fluid dielectric material precursor, such as a polyarylene ether-based resin, is applied to the wafer to backfill the metal network with low-k fluid-based dielectric material.

Abstract: An integrated circuit includes an electronic fuse (“E-fuse”) cell having a fuse link and an E-fuse programming current generator. The fuse link has a width (FLw) and a thickness (FLT) and is fabricated from a layer of link material. An E-fuse programming current generator includes a reference link array having a plurality of reference links. Each of the reference links has the fuse link width and the fuse link thickness, and is fabricated from the layer of link material.

Abstract: An integrated circuit has a differential I/O buffer (102) capable of being operated in a single-ended mode. The I/O buffer includes circuitry (114 or 112) for reducing leakage current between the differential I/O pins (P, N) when an undershoot event occurs on a pin when operated single-ended mode. In one case, a differential termination circuit (114, 200) includes a differential termination isolation circuit (202) that isolates the termination load (201) and termination load switch (208) from the single-ended pin. Alternatively or additionally, a differential output driver (300) of the I/O buffer switches a common bias voltage (ncom) to a supply voltage (VCOO) in single-ended mode to insure the transistors (A2, B1) in the driver legs remain OFF during an undershoot event.

Abstract: An electronic fuse memory array has an array core with a plurality of selectable unit cells. A unit cell has a fuse and a cell transistor (M12). A programming current path goes through the fuse and the cell transistor to a word line ground and a read current path also goes through the fuse and the cell transistor to the word line ground.

Abstract: An electrically erasable programmable read-only memory (“CMOS NON-VOLATILE MEMORY”) cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Abstract: A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Abstract: Recesses are formed in the drain and source regions of an MOS transistor. The recesses are formed using two anisotropic etch processes and first and second sidewall spacers. The recesses are made up of first and second recesses, and the depths of the first and second recesses are independently controllable. The recesses are filled with a stressed material to induce strain in the channel, thereby improving carrier mobility. The widths and depths of the first and second recesses are selectable to optimize strain in the channel region.

Abstract: Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Abstract: A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

Abstract: A static random access memory (“SRAM”) has a plurality of SRAM cells connected to a word line. A static noise margin (“SNM”) detector controls a pull-down transistor that selectively couples the word line to a ground path. The SNM detector is configured to produce a first output signal in response to a SNM event that couples the word line to the ground path, and otherwise produces a second output signal that de-couples the word line from the ground path.

Abstract: A method of testing a semiconductor wafer having a test structure performs an E-beam stress scan of the test structure in an E-beam system to electrically stress the test structure to produce a stress defect. An inspection scan is performed in the E-beam system to identify the stress defect.

Abstract: A receiver has a first input port and a second input port both coupled to a differential amplifier through first and second input capacitors. A bias circuit coupled to the core side of the first input capacitor and to the core side of the second input capacitor is configured to provide a selected voltage to at least one of the first input and the second input of the differential amplifier. In one embodiment, a common mode bias circuit provides a common mode voltage to both inputs of a differential amplifier. In a particular embodiment, a run length detector monitors the output of the differential amplifier and provides a run length feedback signal or an average bit density feedback signal to the set the selected voltage between periods of data reception.

Abstract: An integrated circuit with an efuse having an efuse link includes a damage detection structure disposed in relation to the efuse so as to detect damage in the IC resulting from programming the efuse. Damage sensing circuitry is optionally included on the IC. Embodiments are used in evaluation wafers to determine proper efuse fabrication and programming parameters, and in production ICs to identify efuse programming damage that might create a latent defect.