Abstract: A method of fabricating a halftone phase shift mask is disclosed, by which a process time and a failure ratio can be reduced by sequentially forming a phase shift layer a first photoresist, a metal layer and a second photoresist over a transparent substrate, performing a process to expose a portion of the metal layer, and then performing an etching process to expose a portion of the substrate using the second photoresist as a mask, and then performing an electron-beam exposure process on a portion of the first photoresist such that electrons contact the surface of the transparent substrate, and then simultaneously developing a portion of the first photoresist and removing a portion of the metal layer and a remaining portion of the first photoresist to expose a portion of the phase shift layer.

Abstract: A semiconductor device, particularly, a method for manufacturing a high voltage semiconductor device is disclosed. The method includes forming a high voltage gate oxide film on a semiconductor substrate having a high voltage device region and a low voltage device region, forming a gate electrode on the semiconductor substrate having the high voltage gate oxide film, forming a fluorinated silicate glass (FSG) film and a liner film sequentially on an entire surface of the semiconductor substrate including the gate electrode, and forming an interlayer insulating film on the liner film. Thus, it is possible to prevent an increase in leakage current of the high voltage semiconductor device such as a MOS transistor.

Abstract: Embodiments relate to a start-up circuit for a reference voltage generation circuit. According to embodiments, a start-up circuit may include a start-up start unit allowing current to flow in the reference voltage generation circuit to initiate a start-up process in response to a start-up start signal, a reference current generation unit decreasing a variable voltage depending on whether the reference voltage generation circuit is started up and generating start-up reference current corresponding to the variable voltage, and a start-up controller detecting current flowing in the reference voltage generation circuit, comparing the detected result with the start-up reference current, and outputting the compared result as a start-up start signal. Current consumption may be decreased after start-up. A BRG circuit may be stably started up. If a high supply voltage is used, current consumption may decrease, and if a low supply voltage is used, a BGR circuit may be stably started up.

Abstract: Embodiments relate to a semiconductor device and a method for manufacturing the same. According to embodiments, a semiconductor device may include an LDD which may include a space having a first width and may be formed in a semiconductor substrate, a channel area which may be formed in the semiconductor substrate within a space having a first width, a gate insulating layer which has a width wider than the first width and may be formed on an upper side of the channel area on the semiconductor substrate, a gate which may be formed with the first width on the gate insulating layer, and a spacer including a first spacer formed at both sides of the gate insulating layer and a second spacer formed at sidewalls of the gate.

Abstract: Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.

Abstract: Embodiments relate to a method of manufacturing an image sensor which includes forming a plurality of lower layers over a semiconductor substrate. A first passivation layer may be formed over the lower layers to protect the lower layers. The first passivation layer may be formed in a pixel region and a peripheral region with different thicknesses. A spin-on-glass (SOG) layer may be formed over the first passivation layer. A second passivation layer may be formed over the SOG layer. Array etching may be used to form a concave area in the semiconductor substrate. A plurality of micro lenses may be formed over the bottom surface of the concave area.

Abstract: Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern.

Abstract: The present invention relates to an apparatus and method for controlling power to a Universal Serial Bus (USB) device. The present invention provides an apparatus for controlling power to a USB device, the USB device being used to connect a Personal Computer (PC) with a peripheral device, the power control apparatus including a plug-in port for connecting the peripheral device with the PC, a state detector for detecting whether the peripheral device is in a preparation completion state, a power supply unit for supplying power to the USB device, and a power control unit for controlling the power supply unit so that power is supplied to the USB device if it is determined that the peripheral device is in a plugged-in state, and if it is determined that the peripheral device is in a preparation completion state by the state detector.

Abstract: A power metal oxide silicon field effect transistor in which sources are connected to each other, a single source supplies electrons to two channels, a contact surface between the source and a channel is variously changed to be maximized such that large current flows in a small area, and an electrical field is not concentrated to a gate edge.

Abstract: A method for designing a driver including matching stages having transistors matched to each other is disclosed, including interpreting an offset caused by a mismatched characteristic difference of a plurality of transistors using a current change in a matching stage. A size of the transistors may be determined using the results of interpreting of the offset, and the size may be adjusted until a simulated yield of the driver obtained by a simulation using measured matching information and the determined size of the transistors approximates a targeted yield. The resulting determined size may be used to fabricate the driver, to obtain a test yield of the manufactured driver. If the test yield is not the targeted yield, the measured matching information may be adjusted until the adjusted yield of the driver obtained by the simulation approximates the test yield.

Abstract: An apparatus that can effectively operate in high temperatures including a CMOS image sensor, a thermoelectric semiconductor formed under the CMOS image sensor for selectively cooling the image sensor and a heat sink formed under the thermoelectric semiconductor.

Abstract: A method for patterning a semiconductor device can include forming a conductive layer over a semiconductor substrate; alternatively forming positive photoresists and negative photoresists over the conductive layer, forming a plurality of first conductive lines by selectively removing a portion of the conductive layer using the positive photoresist and the negative photoresist as masks; forming an oxide film over the semiconductor substrate including the first conductive lines and the conductive layer; performing a planarization process over the oxide film using the uppermost surface of the first conductive line as a target; removing the plurality of first conductive lines using the oxide film as a mask; forming a plurality if trenches in the semiconductor substrate and removing a portion of the oxide film to expose the uppermost surface of the conductive layer; and then forming a plurality of second conductive lines by removing the exposed conductive layer using the oxide film as a mask.

Abstract: Disclosed is a superconducting power cable capable of quench detection, and a quench detection system using the superconducting power cable. The superconducting power cable capable of quench detection includes a former; a superconducting conductor layer composed of a superconducting wire and surrounding the former; a conductor layer quench detection coil interposed between the former and the superconducting conductor layer and surrounding the former; an insulating layer surrounding the superconducting conductor layer; and a shielding layer surrounding the insulating layer. This superconducting power cable may detect quench generated during its operation in real time.

Abstract: A flash memory device may include a device isolation layer and an active area formed over a semiconductor substrate, a memory gate formed over the active area, and a control gate formed over the semiconductor substrate including the memory gate, wherein the active area, where a source contact is to be formed, has the same interval spacing as a bit line, and a common source line area, where the source contact is to be formed, has an impurity area connecting neighboring active areas.

Abstract: According to embodiments, an insulated gate bipolar transistor (IGBT) may include a first conductive type collector ion implantation area, formed within a substrate, second conductive type first buffer layers, formed over the collector ion implantation area and each including a first segment buffer layer and a second segment buffer layer, a first conductive type poly layer formed from a surface of the substrate to the collector ion implantation area, the first conductive type poly layer having a contact structure, a second buffer layer of the second conductive type, formed in the substrate area next to the first conductive type poly layer. According to embodiments, a segment buffer layer may have different concentrations according areas. Accordingly, amounts of hole currents injected through the buffer layers may differ according to areas.

Abstract: A method for manufacturing a capacitor of a semiconductor device includes forming a lower metal layer over a substrate, forming a dielectric layer over the lower metal layer, forming an upper metal layer over the dielectric layer, forming an upper electrode and a dielectric layer pattern by performing a reactive ion etching process with respect to the upper metal layer using the dielectric layer as an etch stop layer, and exposing a top surface of the lower metal layer, and performing a chemical down-stream etch (CDE) process to remove a by-product of a sidewall of the upper electrode.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A semiconductor device and a method for manufacturing the device capable of preventing an LDD region and a lower portion of the gate electrode from overlapping each other to achieve desirable device performance are disclosed. Embodiments relate to a semiconductor device and a method for manufacturing the device that may minimize overlap between an LDD region and a lower portion of the gate electrode. Minimizing overlap may maximize device performance and minimize the generation of defects between gate electrodes.

Abstract: An image sensor and fabricating method thereof for preventing cross-talk between neighboring pixels by providing at least three light-shield walls combining to extend vertically above a lateral periphery of a photodiode for deflecting light from a microlens array towards the photodiode.

Abstract: A method for manufacturing a CMOS transistor includes preparing a silicon substrate provided with a first buried layer, a second buried layer and a body, vertically forming device-isolation films inside the body, forming a first-type well inside the body arranged on the first buried layer, and vertically forming a first source and drain region inside the first-type well, forming a second-type well inside the body arranged on the second buried layer, and vertically forming a second source and drain region inside the second-type well, and vertically forming a recessed gate between the first-type well and the second-type well.