Patents Represented by Attorney Skjerven Morrill LLP
  • Patent number: 7149991
    Abstract: A method is taught for determining a calibrated wire load model. The calibrated wire load model can be used to reach timing closure for an integrated circuit. The method includes; determining a reference timing description; determining a wire load model based on synthesis; determining a wire load model based connectivity; comparing the wire load model based on connectivity to the reference timing description. The method teaches adjusting the wire load model based on connectivity to determine a wire load model which faciliates timing closure. The method also teaches comparing the wire load model (based on synthesis) with the reference timing description. The disclosure contemplates a computer program product based upon the method taught. The disclosure further contemplates an integrated circuit designed based on the method taught. In another embodiment a computer system or another electronic system includes an integrated circuit designed by the method taught.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: December 12, 2006
    Assignee: NEC Electronics America, Inc.
    Inventors: Attila Kovacs-Birkas, Wolfgang Roethig, Nader J. Haddad
  • Patent number: 7053419
    Abstract: Light emitting devices with improved light extraction efficiency are provided. The light emitting devices have a stack of layers including semiconductor layers comprising an active region. The stack is bonded to a transparent lens having a refractive index for light emitted by the active region preferably greater than about 1.5, more preferably greater than about 1.8. A method of bonding a transparent lens to a light emitting device having a stack of layers including semiconductor layers comprising an active region includes elevating a temperature of the lens and the stack and applying a pressure to press the lens and the stack together. Bonding a high refractive index lens to a light emitting device improves the light extraction efficiency of the light emitting device by reducing loss due to total internal reflection. Advantageously, this improvement can be achieved without the use of an encapsulant.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: May 30, 2006
    Assignee: LumiLeds Lighting U.S., LLC
    Inventors: Michael D. Camras, Michael R. Krames, Wayne L. Snyder, Frank M. Steranka, Robert C. Taber, John J. Uebbing, Douglas W. Pocius, Troy A. Trottier, Christopher H. Lowery, Gerd O. Mueller, Regina B. Mueller-Mach
  • Patent number: 6992725
    Abstract: A de-interlacing architecture is taught. The de-interlacing architecture adopts a perceptual model to measure membership probabilities for a collection of image samples of an interlaced video source with respect to extracted static, motion, and texture image components of the same collection. The probabilities are used to prioritize contributions from the three image components and produce a progressive video sequence which is a summation of the portions of the aforementioned components. The perceptual model uses a dual-stage motion-based image difficulty measuring scheme to equalize contributions from the three image components in a manner that video artifacts in the output signal are least perceptive. A parameter mapping technique composed of several logic units, a decision function, a weight assignment block, and a look-up table, will be presented to derive the final component weights.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: January 31, 2006
    Assignee: NEC Electronics America, Inc.
    Inventor: Nader Mohsenian
  • Patent number: 6985843
    Abstract: The invention relates to a method for modeling an input/output cell located on the perimeter of an integrated circuit. A method is taught to model an the integrated circuit when sufficient area is not available on the perimeter of the integrated circuit. The input/output cell can be modeled in two locations; one location on the perimeter of the cell and a second location in the interior area, or core, of the integrated circuit. The model uses a cover to prevent the area of the core of the integrated circuit from being used for other purposes. When the input/output cell is divided into a main cell and more than one pre-cell, the model uses a cover for each pre-cell. The model adjusts the timing of the signals to compensate for the input/output cell being divided into two areas. In an embodiment a software tool performs the functions of the model.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: January 10, 2006
    Assignee: NEC Electronics America, Inc.
    Inventor: Attila Kovacs-Birkas
  • Patent number: 6859508
    Abstract: A multidimensional equalizer and cross talk canceller for a communication network that simultaneously removes far end cross talk NEXT) and intersymbol interference (ISI) from a received signal. A multidimensional-pair channel is treated as a single multidimensional channel and a receiver in the communication network equalizes received signals through the use of the multidimensional equalizer. A decision feedback equalizer determines a multidimensional steepest descent gradient to adjust matrix coefficients.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: February 22, 2005
    Assignee: NEC Electronics America, Inc.
    Inventors: Tetsu Koyama, Jason Peng, Paul E. Cohen
  • Patent number: 6782502
    Abstract: A method and apparatus that couple a change input scan chain test pattern with an initialization scan chain test pattern such that a resultant scan chain test pattern is produced, and apply the resultant scan chain test pattern to at least one combinational logic path. In one embodiment, the coupling is achieved by interleaving the change input scan chain test pattern with the initialization scan chain test pattern. In another embodiment, the coupling is achieved by creating a constructed test pattern set from the change input and the initialization scan chain test pattern.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: August 24, 2004
    Assignee: NEC Electronics, Inc.
    Inventor: Wern-Yan Koe
  • Patent number: 6766212
    Abstract: A method and system for use in wafer fabrication systems. The method and system identify relationships among constituent parts of a wafer fabrication system by generating a presentation of at least one relationship between an identified at least one integral part associated with the wafer fabrication system and at least one other integral part associated with the wafer fabrication system.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: July 20, 2004
    Assignee: NEC Electronics, Inc.
    Inventor: Timothy C. Dean
  • Patent number: 6728590
    Abstract: A method and system for use in wafer fabrication systems. The method and system identify wafer fabrication system impacts resulting from specified actions by specifying at least one action related to at least one integral part associated with the wafer fabrication system, and generating a presentation of at least one impact upon at least one integral part associated with the wafer fabrication system arising from the at least one action related to the at least one integral part associated with the wafer fabrication system.
    Type: Grant
    Filed: July 14, 1999
    Date of Patent: April 27, 2004
    Assignee: NEC Electronics, Inc.
    Inventor: Timothy C. Dean
  • Patent number: 6715040
    Abstract: Described is a data processing system including a processor, a plurality of caches, and main memory, the secondary caches being implemented as being non-inclusive, i.e., the lower order caches not storing a superset of the data stored in the next higher order cache. The non-inclusive cache structure provides increased flexibility in the storage of data. The operation of a write request operation when the target data line is not found in the primary cache. By using the dirty bit associated with each data line, the interaction between the processor and the primary cache can be reduced. By using the invalidity bit associated with each data line, the interaction between the processor and the primary cache can be reduced.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: March 30, 2004
    Assignee: NEC Electronics, Inc.
    Inventors: Jin Chin Wang, Maciek P. Kozyrczak
  • Patent number: 6639303
    Abstract: To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insulator at the via bottoms, the insulator is etched slower than the wafer material (e.g. silicon). Therefore, when the dielectric is etched off and the metal is exposed, the dielectric protrudes down from the wafer back side around the exposed metal contact pads, by about 8 &mgr;m in some embodiments. The protruding dielectric portions improve insulation between the wafer and the contact pads when the contact pads are soldered to an underlying circuit. In some embodiments, before the contact pads are soldered, additional dielectric is grown on the wafer back side without covering the contact pads.
    Type: Grant
    Filed: December 17, 1999
    Date of Patent: October 28, 2003
    Assignee: Tru-Si Technolgies, Inc.
    Inventor: Oleg Siniaguine
  • Patent number: 6633494
    Abstract: A charge pump system, including a charge pump and associated distributed clock generation circuitry, is provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and a two-stage charge pump. The two phase bootstrapping circuits are both responsive to the clock and use a distributed bootstrapping scheme to provide first and second phase clock signals with fixed multiples of the power supply voltage in order to overcome increased effective transistor threshold voltages, increase efficiency, and allow for charge boosting in a limited number of stages. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: October 14, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Bob Roohparvar, Kevin Z. Mahouti, Karl Rapp
  • Patent number: 6627901
    Abstract: An apparatus and method for distributing dopant gas or vapor in an arc chamber of ion source used as part of an ion implanter. The apparatus includes a plenum, a sub-plenum, and a baffle to distribute the dopant gas or vapor through out the arc chamber. The method allows dopant gas and vapors to be distributed in such a way as to cause efficient reaction of dopant gas or vapor molecules with electrons created by a filament contained in the arc chamber. The reaction of dopant gas or vapor molecules with the electrons in turn produces positively charged ions by the ion implanter.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: September 30, 2003
    Assignee: NEC Electronics, Inc.
    Inventor: Christopher D. Martinez
  • Patent number: 6625781
    Abstract: The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: September 23, 2003
    Assignee: NEC Electronics, Inc.
    Inventors: Wolfgang Roethig, Ganesh Lakshminarayana, Anand Raghunathan, Arun Balakrishnan
  • Patent number: 6622283
    Abstract: In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A.new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder. The convolutional decoding can be implemented with a digital signal processor and a dedicated peripheral unit. This apparatus can provide an efficient use of memory for the possible decoding paths.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 16, 2003
    Assignee: NEC Electronics, Inc.
    Inventor: Paul E. Cohen
  • Patent number: 6608994
    Abstract: Broadcast programs, e.g., for an audio information program, are divided into one or more segments and are broadcast to a receiver in packet format. The receiver captures the transmitted packets and reassembles the segments and the program for storage and subsequent output to the user. Segment quality of service is evaluated prior to output by ensuring that a minimum percent of packets per segment are usable, and by ensuring that no more than a maximum number of consecutive packets in the segment are unusable. Program quality of service is evaluated by ensuring that a minimum percent of segments per program are usable, and by determining if the first and/or last segment is usable. Different quality of service parameters are specified for particular programs. New quality of service parameters for particular programs are transmitted to the receiver.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: August 19, 2003
    Assignee: Command Audio Corporation
    Inventors: Albert W. Wegener, Orlando Martinez, Edward J. Costello, Jonathan Voichick, Eric X. Wen, Thomas M. Linden
  • Patent number: 6606589
    Abstract: Disclosed is a solid state disk emulator system for significantly improving access time, i.e., improving both the seek time and the rotational latency. The disk emulator complies with the SMD interface convention and thus to the central processor and the SMD disk controller, the disk emulator appears as a disk with virtually a zero access time. In one embodiment, the primary systems of the disk emulator are a 66-bit shift register, a parity circuit, a latch circuit, a 66-bit parallel bus and a dynamic random access memory (DRAM) array. Each of these systems interface with control systems of the disk emulator which provide the signals required for the read and write operations of the disk emulator. An error correction process is incorporated in the disk emulator which corrects single bit hard memory errors using only a single parity bit.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: August 12, 2003
    Assignee: Database Excelleration Systems, Inc.
    Inventors: George B. Tuma, Wade B. Tuma, Robert E. Warne
  • Patent number: 6599804
    Abstract: Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: July 29, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 6598050
    Abstract: An enhanced translation lookaside buffer (TLB), which translates a virtual address into a physical address, permits sharing of data or programs among a subset of all tasks through the use of a group membership field. Each entry in the TLB includes a global bit indicating that all tasks should have access to the translation, an address space identifier identifying an individual task that should have access to the translation and a group membership field identifying a group of tasks that have access to the entry, wherein the group of tasks is a subset of all tasks. The virtual address also has a group membership field that is compared with a group membership field in the TLB entry. If the two group membership fields match, the current task is permitted to use the translation. Thus, a given translation within the TLB may be valid for all tasks, only an individual task, or a group of tasks.
    Type: Grant
    Filed: February 11, 2000
    Date of Patent: July 22, 2003
    Assignee: Integrated Device Technology, Inc.
    Inventor: Philip A. Bourekas
  • Patent number: 6593653
    Abstract: A silicon carbon nitride (SiCN) layer is provided which has a low leakage current and is effective in preventing the migration or diffusion of metal or copper atoms through the SiCN layer. The SiCN layer can be used as a diffusion barrier between a metal portion (such as a copper line or via) and an insulating dielectric to prevent metal atom diffusion into the dielectric. The SiCN layer can also be used as an etchstop or passivation layer. The SiCN layer can be applied in a variety ways, including PECVD (e.g., using SiH4, CH4, and NH3) and HDP CVD (e.g.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: July 15, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Srinivasan Sundararajan, Mayur Trivedi
  • Patent number: 6589801
    Abstract: A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: July 8, 2003
    Assignee: Amkor Technology, Inc.
    Inventors: Ju-Hoon Yoon, Dae-Byung Kang, In-Bae Park, Vincent DiCaprio, Markus K. Liebhard