Abstract: A method is disclosed for manufacturing chip-scale semiconductor packages at a wafer-scale level using wafer mapping techniques. In the method, a semiconductor wafer and/or a circuit substrate, each respectively comprising a plurality of individual chips and circuit pattern units, is/are pre-tested and discriminated in terms of the quality and/or grade of each individual chip unit and/or circuit pattern unit contained therein. The test results are marked on the lower surface of each chip unit and/or on each pattern unit. The substrate is laminated to the wafer to form a laminated assembly prior to performing the packaging process, which typically includes a wire bonding step, an encapsulation step and a solder ball welding step. A plurality of connected package units are thereby formed in the laminated substrate-wafer assembly. The package units are then singulated from each other and the laminated assembly by a cutting process.

Abstract: Two or more defect maps may be provided for the same sample surface at different detection sensitivities and/or processing thresholds. The defect maps may then be compared for better characterization of the anomalies as scratches, area anomalies or point anomalies. This can be done without concealing the more significant and larger size defects amongst numerous small and immaterial defects. One or more defect maps can be used to report the anomalies with classified information; the results from this map(s) can be used to monitor the process conditions to obtain better yield.

Abstract: Methods for forming packages for housing an integrated circuit device are disclosed. In one embodiment, a plastic sheet having an first surface is provided. An array of package sites is formed on the first surface of the plastic sheet. The package sites each include a metal die pad and leads surrounding the die pad. The package sites may be formed by applying a first metal layer on the first surface of the plastic sheet, and then applying a second metal layer in a pattern that defines the die pads and leads of the package sites. The first metal layer is then selectively etched using the second metal layer as an etch mask. Next, an integrated circuit die is placed on each die pad of the array. The die is electrically connected to the leads surrounding the respective die pad. An encapsulant is applied onto the first surface of the plastic sheets so as to cover the package sites.

Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract: Methods and structures are provided which support spacer walls in a position which facilitates installation of the spacer walls between a faceplate structure and a backplate structure of a flat panel display. In one embodiment, spacer feet are formed at opposing ends of the spacer wall. These spacer feet can be formed of materials such as ceramic, glass and/or glass frit. The spacer feet support the corresponding spacer wall on the faceplate (or backplate) structure. Tacking electrodes can be provided on the faceplate (or backplate) structure to assert an electrostatic force on the spacer feet, thereby holding the spacer feet in place during installation of the spacer wall. The spacer wall can be mechanically and/or thermally expanded prior to attaching both ends of the spacer wall to the faceplate (or backplate) structure. The spacer wall is then allowed to contract, thereby introducing tension into the spacer wall which tends to straighten any inherent waviness in the spacer wall.

Abstract: A characteristic of a surface is measured by illuminating the surface with optical radiation over a wide angle and receiving radiation reflected from the surface over a wide angle. An emissivity measurement can then be made for the surface, and, alternatively, if a reflectivity measurement is made, it becomes more accurate. One application is to measure the thickness of a layer or layers, either a layer made of transparent material or a metal layer. A one or multiple wavelength technique allow very precise measurements of layer thickness. Noise from ambient radiation is minimized by modulating the radiation source at a frequency where such noise is a minimum or non-existent. The measurements may be made during processing of the surface in order to allow precise control of processing semiconductor wafers, flat panel displays, or other articles. A principal application is in situ monitoring of film thickness reduction by chemical-mechanical-polishing (CMP).

Abstract: Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Abstract: To furnish an IGFET (120 or 122) with an asymmetrically doped channel zone (144 or 164), a mask (212) is provided over a semiconductor body and an overlying electrically insulated gate electrode (148P or 168P). Ions of a semiconductor dopant species are directed toward an opening (213) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

Abstract: An improved flash EEPROM memory-based storage subsystem includes one or more flash memory arrays, each with three data registers and a controller circuit. During a flash program operation, one data register is used to control the program operation, a second register is used to hold the target data value, and a third register is used to load the next sector's data. Subsequent to a flash program operation, a sector's data are read from a flash array into the first data register and compared to the target data stored in the second register. When the data is verified good, the data from the third register is copied into the first and second registers for the next program operation. This creates an improved performance system that doesn't suffer data transfer latency during program operations that require data verification after the program operation is complete. Alternate embodiments perform the comparison using two register implementations and a single register implementations.

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract: An apparatus and method for implementing a decoder for convolutionally encoded symbols (e.g., a viterbi decoder) is described. In one embodiment, a file of all the initial states (or their equivalents) and the nth surviving states associated with the initial states is stored along with the path metric. The initial states (or their equivalents) are an index to a previous file. A new file or files are then generated. An appropriate criterion is utilized to select a final surviving state. The path can be traced back through a plurality of files and the “most likely” path determined. The identifying binary numbers of the final states of each file and the binary numbers of an original initial state determine the “most likely” sequence of convolutionally-encoded symbols received by the decoder.

Abstract: A slot machine is described which allows a player to participate in an additional game of chance whenever a winning combination of symbols includes a special bonus multiplier symbol. In such instances, the award for the winning combination is multiplied by a randomly determined value, thereby increasing the attractiveness of the game. In the preferred embodiment, the bonus multiplier is selected using a weighted random number generator.

Abstract: Embodiments of semiconductor packages containing a stack of at least two semiconductor chips are disclosed, along with methods of making the same. One embodiment includes a substrate, which may be a ball grid array substrate or a metal leadframe. The stack of semiconductor chips is mounted to the substrate. Each semiconductor chip has a plurality of bond pads on an active surface thereof. The bond pads of the first semiconductor chip face corresponding ones of the bond pads of the second semiconductor chip, and are joined thereto through an electrically conductive joint. One of a plurality of bond wires extend from each of the joints to the substrate. Accordingly, pairs of bond pads of the first and second semiconductor chips are electrically interconnected, and are electrically connected to the substrate through the respective bond wire.

Abstract: A programmable circuit, such as a field programmable gate array, and a dedicated device, such as an ASIC type device, are coupled together with an antifuse based interface on a single integrated circuit. A configurable non-volatile memory that communicates with the dedicated device is also located on the integrated circuit. The platform for the programmable circuit is one half of an existing programmable circuit, which eliminates the need to engineer the programmable circuit. The programmable circuit includes a clock network that receives clock signals from clock terminals as well as from a clock network in the dedicated device. The interface between the dedicated device and programmable circuit includes a number of conductors with buffers with testing circuitry. The testing circuitry includes a PMOS test transistor and a NMOS test transistor which permits testing of the buffers without programming the antifuses coupled to the conductors.

Abstract: A widely-used data definition language such as the Extensible Markup Language is used to implement a tuple space-based coordination mechanism. Entries and template entries can represent any type of networked or network-proxied resource, object or service. Using this framework, diverse entry spaces can be aggregated and operated upon as though they were a single large entry space. The flexibility and power of XML constructs can be leveraged to make such aggregation straightforward and efficient.

Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

Abstract: A multiple die package is formed, which allows multiple die to be interconnected using internal leads or traces from a lead frame. A plurality of slots in the paddle area of the lead frame are created which define the internal signal traces. Then the outer portions of the die paddle area of the lead frame are removed or trimmed to isolate the internal traces from each other and form a plurality of individual internal leads. Multiple die, either stacked, in a planar array, or a combination of the two, are connected to selected internal leads, such as by wire bonding, to form the desired die-to-die interconnections for routing signals between die without interfering with normal wire bond fan-out. A tape can be adhered to the interior portion of the die paddle area prior to trimming to hold the internal traces in place and leave the ends of the traces exposed for wire bonding to the die.

Abstract: A system for improving manufacture, said system including but not limited to a Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle. In one embodiment, the Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle further includes but is not limited to the Polyimide solvent dispensing nozzle coupled with a bracket assembly adjustable in three dimensions. In one embodiment, the Polyimide solvent dispensing nozzle coupled with a bracket assembly adjustable in three dimensions further includes but is not limited to a bracket assembly adjustable in an x-axis direction, y-axis direction, and z-axis direction. In one embodiment, the Polyimide solvent dispensing nozzle proximate to a Polyimide dispensing nozzle further includes but is not limited to the Polyimide solvent dispensing nozzle mounted on an arm holding the Polyimide dispensing nozzle.