Abstract: The rate of discharge of the sense amplifier and bit lines in a memory circuit is controlled to simulate a boosted sense ground potential without requiring the use of a voltage regulator or precharged capacitors. The sense amplifier is electrically coupled to ground through a large transistor during a first period, which quickly discharges the sense amplifier toward ground potential to ensure a fast sense speed of the sense amplifier. During a subsequent period, the large transistor is turned off and the sense amplifier is electrically coupled to ground through a smaller transistor. The small transistor slowly discharges the sense amplifier towards ground, without reaching ground, until the active cycle is over and the discharge of the sense amplifier is terminated. By holding the sense amplifier above, but near, ground potential, the subthreshold leakage of non-selected memory cells is minimized so that the frequency of refresh may be decreased, thereby minimizing standby current.

Abstract: An inductively-coupled hydrogen plasma (ICP) is used to passivate a plasma-enhanced chemical vapor deposition reactor following an in situ cleaning step. The hydrogen ICP effectively removes the fluorine and hydrogen that typically become impregnated in the walls of the reaction chamber during the in situ clean and thereby reduces the amount of “outgassing” that occurs during subsequent deposition cycles. This outgassing may cause the film of deposition material that normally forms on the walls to flake, significantly reducing the yield of usable devices. The hydrogen ICP passivation process has been found particularly effective in conjunction with the deposition of heavily-doped silicon oxide layers.

Abstract: The present invention relates to chemical modifications of the surfaces of silicalite and high-silica zeolite nanoparticles permitting such particles to be dispersed in nonpolar hydrophobic solvents, and to the dispersions so produced and to interlayer dielectric layers, molecular sieve membranes and/or catalytic membranes formed from such dispersions, and to the fabrication of integrated circuits in the case of interlayer dielectric layers. A dispersion of silicalite or high-silica zeolite nanoparticles is formed in alkaline aqueous solution. The pH of the solution is reduced by multiple rinsing with deionized water to approximately pH of 9 or 10. The solution is then rendered acidic, typically pH between 2 and 3, by the addition of a suitable acid. The acidic solution is gradually intermixed with an alcohol under conditions of elevated temperature and/or reduced pressure to enhance the solvent evaporation rate.

Abstract: A specialized physical vapor deposition process provides dense amorphous semiconducting material with exceptionally smooth morphology. In particular, the process provides dense, smooth amorphous silicon useful as a hard mask for etching optical and semiconductor devices and as a high refractive index material in optical devices. DC sputtering of a planar target of intrinsic crystalline semiconducting material in the presence of a sputtering gas under a condition of uniform target erosion is used to deposit amorphous semiconducting material on a substrate. DC power that is modulated by AC power is applied to the target. The process provides dense, smooth amorphous silicon at high deposition rates. A method of patterning a material layer including forming a hard mask layer of amorphous silicon on a material layer according to the present DC sputtering process is also provided.

Abstract: An ESD structure is created on an integrated circuit by providing a conductive polymer material between a signal line and a supply node or ground reference. The conductive polymer material becomes conductive when an electric field of sufficient intensity is applied. In one embodiment, the concentration of conductive particles of the conductive polymer material is empirically determined so that the resulting film becomes conducting at a predetermined threshold voltage. The conductive polymer is applied in liquid form on the wafer surface using a silk-screen printing process or a spin-on process and then cured. The conductive polymer layer can be adapted for use in multilevel metallization systems.

Abstract: A semiconductor package and a method and a substrate for making the package are disclosed. The substrate of an exemplary package includes metal circuit patterns covered by a layer of an insulative nonphotoimageable solder mask material. A plurality of apertures are formed by laser ablation through the nonphotoimageable solder mask layer so as to expose a selected region of at least some of the circuit patterns. A bond wire is electrically connected between a semiconductor chip connected to the substrate and the respective circuit patterns through the laser-formed aperture over the circuit pattern.

Abstract: A trench-gated power MOSFET contains a highly doped region in the body region which forms a PN junction diode with the drain at the center of the MOSFET cell. This diode has an avalanche breakdown voltage which is lower than the breakdown voltage of the drain-body junction near to the wall of the trench. Thus the MOSFET breaks down in the center of the cell avoiding the generation of hot carriers that could damage the gate oxide layer. The drain-body junction is located at a level which is above the bottom of the trench, thereby avoiding any deep diffusion that would increase the cell width and reduce the cell packing density. This compact structure is achieved by limiting the thermal budget to which the device is exposed after the body region is implanted. As a result, the body and its highly doped region do not diffuse significantly, and dopant from the highly doped region does not get into the channel region of the device so as to increase its threshold voltage.

Abstract: Steering and bit lines (of a flash EEPROM system, for example) are segmented along columns of a memory cell array. In one embodiment, the steering and bit lines of one of their segments are connected at a time to respective global steering and bit lines. The number of rows of memory cells included in individual steering gate segments is a multiple of the number of rows included in individual bit line segments in order to have fewer steering gate segments. This saves considerable circuit area by reducing the number of segment selecting transistors necessary for the steering gates, since these transistors must be larger than those used to select bit line segments in order to handle higher voltages. In another embodiment, local steering gate line segments are combined in order to reduce their number, and the reduced number of each segment is then connected directly with an address decoder, without the necessity of a multiplicity of large switching transistors outside of the decoder to select the segment.

Abstract: A linear regulator circuit includes an input terminal for receiving an input voltage and an output terminal for providing an output voltage. A pass device, coupled to the input terminal and the output terminal, generates an output current. A feedback circuit is coupled to the pass device and the output terminal. The feedback circuit increases the output voltage as the output current decreases and decreases the output voltage as the output current increases.

Abstract: In fabrication of integrated circuits, trenches (184) are formed in a dielectric (170), then a metal (e.g. tungsten or copper) is deposited. The metal (194) is removed from the top surface of the dielectric by a polishing process (e.g. CMP). The metal remains in the trenches. The inventor has discovered that the erosion of the structure in the polishing process does not strongly depend on the size of the structure. Therefore, the erosion of a large structure (440) can be estimated by measuring the erosion of a smaller test structure (450). The erosion of the test structure is measured by a probe instrument (230), e.g. a stylus profilometer or a scanning probe microscope. Use of the test structure reduces the probability of damaging the larger structure by the probe. Other embodiments are also provided.

Abstract: A controlled material transport system (MTS) for carrying materials to and from workstations, test equipment, and processing and assembly tools in a common facility. The present invention includes a rigid robot vehicle mountable to a passive track system, which can be routed to service all processing tools on the factory floor. The robot vehicle includes a hoist assembly and gripper assembly, which together perform such functions as picking up magazines, placing magazines, and loading magazines into the processing tools. The hoist assembly is capable of functioning in an operational envelope, which includes any target location within a 3-axis Cartesian coordinate system, to the extent of the range of motion of the hoist assembly. The hoist assembly also provides rigid and controlled z-axis travel, while being compact when retracted. The gripper assembly facilitates loading of the magazines, especially chute style magazines, which are commonly found on many existing processing tools.

Abstract: A novel semiconductor package comprises a rigid dielectric, e.g., ceramic, substrate having first and second portions joined to one another at respective margins thereof to form an angle, e.g., a right angle, between the portions. Each of the portions has electrically conductive paths connected to one another through the angle. A semiconductor device, e.g., a die, is mounted to the first portion and electrically connected to the conductive paths thereof. An array of electrically conductive lands, balls, or pins are mounted on the second portion for connecting the package to a printed circuit board. In a high-power embodiment, the device is mounted directly on a threaded stud projecting from the first portion to enable intimate thermal coupling of the device to a heat sink. In another embodiment, a connector projects from the first portion to optically couple an optical device directly to an end of a fiber optic cable.

Abstract: A semiconductor package incorporates spacer strips enabling one or more semiconductor dies having central terminal pads to be stacked on top of one another within the package and reliably wire bonded to an associated substrate without shorting of the bonded wires. Each of the spacer strips comprises a flat, elongated strip of an insulative material that mount at edges of a surface of a die such that they straddle the central terminal pads thereon. The die is electrically connected to the substrate by a plurality of fine conductive wires having a first end bonded to one of the central terminal pad on the die, a second end bonded to a terminal pad on the substrate, and an intermediate portion between the first and second ends that passes transversely across the top surface of one of the spacer strips. The spacer strips have spaced pads or grooves on or in their top surfaces that captivate the individual wires and thereby redistribute the wires and prevent them from contacting the die and each other.

Abstract: An efficient NAND array structure includes memory cells coupled in series between a bit-line and a select source transistor, without a select drain transistor. The memory cells each include a floating gate transistor, having a control gate connected to a word-line, which selects the memory cell during its programming. In one embodiment, the NAND array structure includes a buried layer at a junction between the substrate and a well in which the memory cells are formed. Programming is achieved using hot electron injection. In one embodiment, multiple memory cells are programmed simultaneously.

Abstract: Semiconductor chip packages having molded plastic substrates and recessed I/O terminals are disclosed, along with methods of making such packages. In an exemplary embodiment, the molded plastic substrate includes a metal interconnect pattern and a plurality of indentations in a surface thereof. Each indentation may include at least one projection. The indentation and any projections therein are covered by a metal lining. A metal contact, which serves as an I/O terminal, is placed in each of the indentations and is fused to the metal lining thereof. A chip is mounted on the substrate and is electrically connected to the metal contacts by the interconnect pattern. The package further includes a lid or hardened encapsulant over the chip.

Abstract: The present invention relates to porous materials, typically xerogels or aerogels, having a low dielectric constant but relatively poor mechanical strength. The present invention relates to polymeric coatings, preferably parylene, coated on inorganic xerogels or aerogels so as to increase the mechanical strength while not substantially degrading the dielectric properties of the resulting coated material. Silica xerogel conformally coated with parylene AF-4 is described.

Abstract: A vacuum sealed package for a semiconductor chip, such as a micro-electromechanical (MEM) chip, is disclosed, along with a method of making such a package. In an exemplary embodiment, the package includes a ceramic substrate and a lid that together define a cavity wherein the chip is mounted. The substrate includes a conductive (e.g., metal) interconnect pattern that extends, at least in part, vertically through the substrate. I/O terminals are provided on an external surface of the substrate. A vent hole, at least partially lined with a metal coating, extends through the substrate into the cavity. A metal plug seals the vent hole. The vent hole is sealed by placing the package in a vacuum chamber, evacuating the chamber, and heating the chamber so as to cause a metal preform on the substrate to flow into the vent hole and form the plug.

Abstract: An improved amplifier circuit is disclosed. In one embodiment, the amplifier circuit includes an amplifier transistor that has a base terminal connected to receive an input signal. The amplifier circuit also includes a reference voltage source that generates a reference voltage at a reference voltage output node. A local bias circuit provides a bias voltage to the base terminal of the amplifier transistor. The local bias circuit includes a first transistor that has an emitter terminal coupled to the reference voltage output node, a collector terminal coupled to a supply voltage node, and a base terminal connected to the collector terminal. The local bias circuit also includes a second transistor that has a base terminal coupled to the base terminal of the first transistor, a collector terminal coupled to the supply voltage node, and an emitter terminal coupled to the base terminal of the amplifier transistor.

Abstract: The invention encompasses methods and apparatus for pumping fluid from one location to another through the repetitive expansion and collapse of bubbles generated as a result of the absorption of repetitive pulses of radiation in a fluid. This pumping phenomenon can be used to aid removal of a total or partial occlusion in a body passage by emulsifying the occlusion with acoustic shock and pressure waves or by causing mechanically disrupting the occlusive material.