Abstract: A method and/or apparatus is capable of performing high accuracy digital level restoration with a high degree of noise immunity provided by a passive clamping stage.

Abstract: A method and apparatus for performing reflectometry using a specific wavelength or a small number of specific wavelengths within a spectral range to detect the presence of a copper oxide film on a substrate or to measure the film thickness is described. A method for analyzing reflectivity data to obtain film thickness is also described. Using the described method and apparatus, reflectometry can be performed using only one or two wavelengths of light so that simple photodiode detectors may be used instead of a complex and costly spectrometer (although a spectrometer may be used to detect the reflected light). Therefore, the described invention can provide in-situ or vacuum integrated metrology with simple, low-cost hardware. Finally, the described method does not require detailed curve fitting and thus the necessary thickness data can be acquired rapidly.

Abstract: An integrated fuse element is capable of being programmed to high resistance in low voltage process technology. The fuse includes a stack of an undoped polysilicon layer and a silicide layer. A voltage applied across the stack is increases until a first agglomeration event occurs, whereby a discontinuity is formed in the silicide layer. The current is further increased to cause a second agglomeration event whereby the size of the discontinuity is increased. Each agglomeration event increases the resistance of the fuse. An extended-drain MOS transistor, capable of sustaining high voltage, is connected in series with the fuse for programming the fuse.

Abstract: A chemical vapor deposition process for depositing tungsten films having small grain size is provided. The process involves depositing a nucleation layer having very small nuclei that are closely spaced so that there are few vacancies on the surface. Such a nucleation layer results in a film with small grains after the subsequent deposition of bulk layers. The temperature of the substrate can be increased during deposition of the nucleation layer and then lowered for deposition of the bulk layer to produce a small grain tungsten film. Additionally, the thickness of the nucleation layer can be controlled, and the deposition chamber pressure and silage flow rates can also be controlled to achieve the desired nucleation layer before deposition of the bulk layers.

Abstract: A 90 percent electron gun aperture astigmatism is used in conjunction with a four-pole electromagnet to make a CRT electron beam just focus point and minimum beam width occur closer to the same focus voltage. A single grid may have the 90 percent astigmatism, or astigmatisms in two or more grids may combine to produce an effective 90 percent astigmatism. A four-pole electromagnet is positioned around the focusing grid and current driving the electromagnet is varied with beam position during normal operation.

Abstract: Method and apparatus for a memory circuit having a sense amplifier circuit having a sensing amplifier connected to read the data content output of a memory cell where the sense amplifier circuit includes a current source transistor having a gate terminal and having a drain terminal connected to a voltage supply and having a source terminal connected to the sensing amplifier, with a selectable source current in order to account for variation from a desired source current due to variations in the designed source current transistor performance parameters.

Abstract: A system of Flash EEprom memory chips with controlling circuits serves as non-volatile memory such as that provided by magnetic disk drives. Improvements include selective multiple sector erase, in which any combinations of Flash sectors may be erased together. Selective sectors among the selected combination may also be de-selected during the erase operation. Another improvement is the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. Yet another improvement is the use of a write cache to reduce the number of writes to the Flash EEprom memory, thereby minimizing the stress to the device from undergoing too many write/erase cycling.

Abstract: A system and method for cardiac mapping and ablation include a multi-electrode catheter introduced percutaneously into a subject's heart and deployable adjacent to various endocardial sites. The electrodes are connectable to a mapping unit, an ablation power unit a pacing unit, all of which are under computer control. Intracardiac electrogram signals emanated from a tachycardia site of origin are detectable by the electrodes. Their arrival times are processed to generate various visual maps to provide real-time guidance for steering the catheter to the tachycardia site of origin. In another aspect, the system also include a physical imaging system which is capable of providing different imaged physical views of the catheter and the heart. These physical views are incorporated into the various visual maps to provide a more physical representation. once the electrodes are on top of the tachycardia site of origin, electrical energy is supplied by the ablation power unit to effect ablation.

Abstract: A method of forming a CMOS structure, the method including the acts of: forming a gate structure over a substrate layer; forming a silicide layer over the substrate layer; forming shallow source/drain areas in the substrate layer; forming an oxide diffusion barrier layer over the structure; forming a metal absorption layer over the oxide diffusion barrier layer; and melting portions of the substrate layer directly overlying the shallow source/drain areas, thereby transforming the shallow source/drain areas into shallow source/drain regions. The act of melting includes the act of exposing the metal absorption layer to pulsed laser beams.

Abstract: The invention provides a method and apparatus for electrically connecting the die of a high power semiconductor device to a substrate with a conductive strap such that the connection is resistant to the shear stresses resulting with changes in temperature. In one embodiment, the method includes providing a substrate having first and second portions that are electrically isolated from each other. A semiconductor die having top and bottom surfaces and one or more active electronic devices formed therein is also provided. The device has a first terminal connected to a first conductive layer on the bottom surface of the die, and a second terminal connected to a second conductive layer on the top surface of the die. The first conductive layer is electrically coupled to a top surface of the first portion of the substrate. The second conductive layer is electrically coupled to the second portion of the substrate with a metal strap.

Abstract: The present disclosure describes a technique that allows the amplitudes of vertical correction signal components to be adjusted independently. When the amplitude of each of the vertical correction signal components are set, they will not have to be readjusted when the amplitudes of the other vertical correction signal components are set. This greatly simplifies the process of setting the amplitudes of the vertical correction signal components, saving time and increasing the accuracy of the settings.

Abstract: A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

Abstract: The present invention is an inverted III-nitride light-emitting device (LED) with enhanced total light generating capability. A large area device has an n-electrode that interposes the p-electrode metallization to provide low series resistance. The p-electrode metallization is opaque, highly reflective, and provides excellent current spreading. The p-electrode at the peak emission wavelength of the LED active region absorbs less than 25% of incident light per pass. A submount may be used to provide electrical and thermal connection between the LED die and the package. The submount material may be Si to provide electronic functionality such as voltage-compliance limiting operation. The entire device, including the LED-submount interface, is designed for low thermal resistance to allow for high current density operation. Finally, the device may include a high-refractive-index (n>1.8) superstrate.

Abstract: A profiler or scanning probe microscope may be scanned across a sample surface with a distance between them controlled to allow the sensing tip to contact the surface intermittently in order to find and measure features of interest. The distance is controlled so that when the sensing tip is raised or lowered to touch the sample surface, there is no lateral relative motion between the tip and the sample. This prevents tip damage. Prior knowledge of the height distribution of the sample surface may be provided or measured and used for positioning the sensing tip initially or in controlling the separation to avoid lateral contact between the tip and the sample. The process may also be performed in two parts: a fast find mode to find the features and a subsequent measurement mode to measure the features. A quick step mode may also be performed by choosing steps of lateral relative motion to be smaller than 100 nanometers to reduce probability of tip damage.

Abstract: A test system includes (a) a tester mechanism (16 and 42) having tester contacts (152) for carrying test signals, (b) an interface module (44), and (c) a device-side board (46) having device-side contacts (162) for connection to external leads of an electronic device (40) under test. The interface module contains a tester-side body (50) having tester-side openings (86) for being positioned opposite the tester contacts, a device-side body (52) having device-side openings (136) for being positioned opposite the device-side contacts, and interface conductors (54) extending through the tester-side and device-side openings for connecting the tester contacts to the device-side contacts. The tester body is configured, typically as at least five wedge-shaped portions (68), in such a manner as to enable the electronic device under test to have an increased number of external leads.

Abstract: A technique for controlling the soft-program current in virtual-ground FLASH memory arrays is described. It is based on biasing the array bit-lines such that all current supplied to the array is used entirely towards the soft-programming of selected cells. The result is control of the soft-programming current and the programming rate of individual cell pairs. The benefit of soft-programming is then realized during the actual cell programming with the improved control of current and program rate. This is described with respect to an embodiment that uses source-side injection as the means for programming memory cells and with respect to a second embodiment based on a cell with dual floating gates.

Abstract: A charge pump system and associated variable-amplitude clock generation circuitry are provided for generating high voltages from a low initial voltage in applications such as erasing and programming electrically erasable programmable read only memory (EEPROM) arrays. The charge pump system uses a power supply voltage and a clock and includes a first phase bootstrapping circuit, an inverter, and a second phase bootstrapping circuit, and charge pump circuitry. The two phase bootstrapping circuits are both responsive to the clock and provide first and second phase clock signals. The inverter is connected to the second phase bootstrapping circuit, causing the second phase clock signal to be opposite in phase from the first clock signal. The charge pump circuitry is responsive to the power supply voltage and the first and second phase clocks and uses native transistors that have lower threshold voltages.

Abstract: Methods of making packages for integrated circuit devices, and in particular for attaching a plurality of integrated circuit die to a substrate strip, are disclosed. The substrate includes a plurality of die mounting sites. A B-staged epoxy film is on each site. An exemplary method includes placing an integrated circuit die on the adhesive film of each site. After a plurality of integrated circuit die are individually placed on the substrate, the adhesive films of a plurality of sites are cured simultaneously in a batch process. The curing permanently attaches the die to the substrate. Subsequently, the die are wire bonded to their respective substrate sites and encapsulated. The encapsulated substrate is cut to form individual packages.

Abstract: A low dropout voltage regulator with non-Miller frequency compensation is provided. The LDO circuit has two wide-band, low-power cascaded operational transconductance amplifiers (OTAs): an error amplifier and a unity-gain-configured voltage follower. The unity-gain-configured voltage follower drives a gate of a power PMOS path transistor with a high parasitic gate capacitance. The wide-band, low-power OTAs enable the use of a single, low-value load capacitor with a low equivalent series resistance (ESR). A frequency compensation capacitor is connected in parallel with the upper resistor of a feedback network, which introduces a zero-pole pair that enhances the phase margin close to unity-loop-gain frequency.

Abstract: Package embodiments for housing an electronic device are disclosed, along with methods of making and interconnecting the packages. The package body may be formed of an injection molded plastic encapsulant. The package body includes a cavity in which the electronic device is contained. A lid extends over the open end of the cavity. Metal leads extend from the package body. A first portion of each lead is at a lower surface of the package body, a second portion of each lead extends vertically adjacent to a peripheral side of the package body, and a third portion of each lead extends over the package lid at a top surface of the package. The package has a key formed in the lid or at the first surface of the package body. The key is adapted so as to engage a corresponding key hole in another package stacked therewith. Abutting leads of the stacked packages form an electrical connection between the packages.