Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. An N drain region is implanted through the bottom of the trench into the P-epitaxial layer, and after a diffusion step extends between the N+ substrate and the bottom of the trench. The junction between the N drain region and the P-epitaxial layer extends between the N+ substrate and a sidewall of the trench. In some embodiments the epitaxial layer can have a stepped doping concentration or a threshold voltage adjust implant can be added. Alternatively, the drain region can be omitted, and the trench can extend all the way through the P-epitaxial layer into the N+ substrate. A MOSFET constructed in accordance with this invention can have a reduced threshold voltage and on-resistance and an increased punchthrough breakdown voltage.

Abstract: To facilitate access of interrupt status information, interrupt posting status. POST.sub.-- STAT registers are readable by a host driver routine to quickly supply information relating to a functional block which has given rise to an interrupt status condition. The interrupt posting status POST.sub.-- STAT registers contain a summary of interrupt status information. The host driver may then read the interrupt posting status POST.sub.-- STAT register corresponding to the functional block to further investigate the cause of the interrupt status. System memory includes a mirror storage of the interrupt posting status POST.sub.-- STAT registers that is transferred to the mirror storage by a direct memory access (DMA) operation. Values in the system mirror storage are updated automatically when a change occurs in a value within the interrupt posting status POST.sub.-- STAT registers. A host system software driver accesses the interrupt posting status POST.sub.

Abstract: A non-volatile programmable latch (110) in an integrated circuit (310) is initialized by an initialization signal (SET). At least a portion of the initialization signal is generated in response to a command to the circuit to perform a circuit initialization operation. In some embodiments, the circuit is a synchronous dynamic random access memory (SDRAM), or a synchronous graphics random access memory (SGRAM). The command is a mode register set command (MRS). The command is received when a predetermined period of time has elapsed after power was turned on. Waiting for the predetermined period of time before initializing the latch allows the voltage powering the latch to develop so that the latch can be initialized reliably.

Abstract: A remote monitoring system automatically communicates system diagnostic information from a monitored computer system to a remote service center at regular intervals. The monitored computer system includes a plurality of monitored computers coupled together by a network. One of the monitored computers is a master and others of the monitored computers are slaves coupled to the master. The monitored computers store system diagnostic information resulting from execution of diagnostic programs. The diagnostic information from the slaves is collected at a memory location accessible by the master before the diagnostic information from all of the monitored computers is communicated to the remote monitoring computer system. The remote monitoring computer system receives the diagnostic information at predetermined intervals and incorporates the diagnostic information into a searchable database.

Abstract: A method for analyzing the channel using the preceding slot synchronization sequence is provided. The method of the invention is for operating a receiver receiving a signal frame in a dynamic channel wherein the signal frame includes a plurality of slots, each including a plurality of data bits. Each of the slots further includes a synchronization sequence wherein at least a predetermined one of the slots is assigned for the receiver. The preceding slot following the receiver assigned slot includes a varying synchronization sequence which is selected from a group of predetermined synchronization sequences postulates. The method includes the steps of calculating from the preceding slot synchronization sequence an estimated taps value for each of the synchronization sequence postulates, calculating from the preceding step synchronization sequence a log likelihood metric value C(y,h) for each of the synchronization sequence postulates and selecting the synchronization word postulate having the best metric value.

Abstract: A programming architecture for a field programmable gate array (FPGA) employing antifuses is disclosed. To test the integrity of programming conductors, programming transistors, routing wire segments and a combinatorial portion of a logic module of the unprogrammed FPGA (see FIG. 16), a combination of digital logic values is supplied onto the inputs of the combinatorial portion in a test mode. A defect is determined to exist if the correct digital value is not then output by the combinatorial portion. The digital value output by the combinatorial portion is captured in the flip-flop of the logic module and is shifted out of the FPGA in a scan out test mode. A programming transistor, programming conductor and routing wire segment structure is also disclosed which facilitates such testing. In one embodiment (see FIG.

Abstract: A method for implanting a dopant into a thin gate electrode layer includes forming a displacement layer on the gate electrode layer to form a combined displacement/gate electrode layer, and implanting the dopant into the combined layer. The implanted dopant profile may substantially reside entirely within the gate electrode layer, or may substantially reside partially within the gate electrode layer and partially within the displacement layer. If the displacement layer is ultimately removed, at least some portion of the implanted dopant remains within the gate electrode layer. The gate electrode layer may be implanted before or after patterning and etching the gate electrode layer to define gate electrodes. Moreover, two different selective implants may be used to define separate regions of differing dopant concentration, such as P-type polysilicon and N-type polysilicon regions.

Abstract: A bit field system is disclosed which includes a processor as well as a bit field peripheral device which is accessed via dedicated bit field addresses. Such a system efficiently executes bit field operations. Additionally, such a system advantageously provides a processor which does not include an original bit field instruction set with the ability of performing bit field operations. Such a system also advantageously avoids difficulties involved in encoding bit field instructions.

Abstract: A block decoder includes a p-well. A low voltage source is coupled to the p-well for asserting a body bias voltage to the p-well. An n-type word line pass transistor is positioned within the p-well and is coupled to a word line for passing programming voltages to the word line. A high voltage source is coupled to pass circuitry configured to assert a voltage on a gate of the pass transistor. The low voltage source is configured to apply a voltage of approximately 10 volts or more to the p-well during programming, thus reducing the voltage between the source and body region (and thus the threshold voltage as well) of NMOS transistors disposed within the p-well. Therefore, the amount of voltage needed to be applied to the pass transistors is reduced. Furthermore, the pass circuitry can work for lower supply voltages since the supply voltage is limited by the threshold voltage of the n-type transistors within the p-well.

Abstract: A carrier head that holds an object such as a wafer for a polishing system can be rotated during polishing. One such carrier head includes a sensor that determines the relative orientation of (or the angle between) a movable chuck and a fixed drive structure. A control system uses these measurements to select the edge pressure applied to the wafer or the chuck to control the attack angle of the wafer against polishing pads. By actively adjusting the attack angle, a carrier head can accommodate torques about an axis not in the plane of contact between the wafer and the polishing pad even when the wafer is otherwise free to rotate about the axis. One carrier head includes a drive plate with projections ending with balls that are disposed in matching openings in a carrier plate. Radial elongation of openings and curvature of the balls permit rotation of the carrier plate about an axis in plane passing between the carrier and drive plates.

Abstract: A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.

Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible patterns and features, and 2) selecting desired patterns and features with a non-precision targeting energy beam or mask. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.

Abstract: An output driver prevents gate oxide breakdown and reverse charge leakage from a bus to the internal power supply. When the voltage on the bus exceeds the internal supply voltage or when the driver is powered down, a reference voltage generator provides intermediate voltages to prevent the development of excessive gate-source, gate-drain, and gate-backgate voltages in the driver. An upper protection circuit and a lower protection circuit multiplex the intermediate voltages to ensure driver protection and proper operation. A buffering circuit turns off a buffering transistor to block charge leakage to the internal power supply when the bus voltage is greater than the internal power supply voltage. A logic protection circuit prevents the bus voltage from appearing at the control terminal of the driver.

Abstract: A system for computing a pattern function for a polygonal pattern having a finite number of predetermined face angles. One method includes the steps of decomposing the polygon into a set of flashes, computing the pattern function by summing together all flashes evaluated at a point (x,y), and the pattern function returning a 1 if point (x,y) is inside a polygon and otherwise will return a 0.

Abstract: A structure and method are provided to compensate for temperature changes on wavelength shifting in DWDM by reducing tension in a fused-fiber DWDM when temperature increases and increasing tension when temperature decreases, thereby stabilizing wavelength shifts throughout the range of operating temperatures. The DWDM, which is enclosed by a protective package in some embodiments, is connected to substrates of different thermal expansion coefficients, such that the fused-fiber portion of the DWDM exhibits negative thermal expansion, i.e. contracts when temperature increases and expands when temperature decreases. As a result, temperature-induced wavelength shifts are minimized due to a passive thermal compensation, which can be easily adjusted. In other embodiments, twisting the fused-fiber portion of the DWDM to obtain optimum phase matching minimizes the polarization-dependent losses in the incoming light.

Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.

Abstract: A multiplier has two input value terminals which receive two signed input bit groups. The multiplier also has two output terminals configured to carry a sum and carry bit group representing, in redundant form, a product of the two signed input values. A sign determining circuit generates a sign bit representing a sign of the product of the two input signed values. An extension unit has three input terminals configured to receive the most significant bit of the sum bit group, the most significant bit of the carry bit group, and the sign bit generated by the sign determining circuit. The extension unit is structure to generate a least significant extension bit and a more significant extension bit. The least significant extension bit has one binary state if the sum most significant bit, the sign bit, and the carry most significant bit have the same binary state. The least significant extension bit otherwise has the opposite binary state.

Abstract: A shared data storage subsystem having a system controller embedded in a backplane of the shared data subsystem. The system controller monitors the TERMPWR signals of SCSI server busses physically coupled to the shared data subsystem to operably couple and isolate a server SCSI bus with the share data subsystem SCSI bus provides. The system can be used to isolate a server from a data storage subsystem without affecting the operation of other servers operably coupled to the data storage subsystem. The servers and shared data subsystem are implemented in a cluster system. The system controller also monitors environmental conditions of the shared data subsystem. The shared data subsystem includes a plurality of data storage devices such as hard disk drives which can be organized in a RAID configuration.

Abstract: An IGFET device isolation structure fabrication scheme includes the formation of electrically insulating isolation structures that extend into the substrate and extend above the surface of the substrate. The isolation structures are formed by providing a first mask to form trenches in the substrate. A layer of silicon dioxide is then deposited, filling the trenches and extending above the surface of the substrate. A second mask layer is formed. The second mask layer shadows the trench regions that were formed in the substrate. The silicon dioxide not shadowed by the second mask layer is removed, leaving isolation structures that extend both into the substrate and which rise above the substrate. A gate structure is formed in the region between two isolation structures, and, in the preferred embodiment, the gate structure extends above the substrate to the same height as the isolation structures. The isolation structures and the gate structure can be used to provide self-aligned doped source/drain regions.